component
SN74LVC541AQPWREP
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LVC541AQPWREP
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74LVC541AQPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable for the first 2-input 3-state AND gate; when OE1 or OE2 is high, all eight outputs are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to ensure high-impedance during power up or power down. |
| 2 | A1 | input | Data input to buffer/driver channel 1; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 3 | A2 | input | Data input to buffer/driver channel 2; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 4 | A3 | input | Data input to buffer/driver channel 3; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 5 | A4 | input | Data input to buffer/driver channel 4; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 6 | A5 | input | Data input to buffer/driver channel 5; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 7 | A6 | input | Data input to buffer/driver channel 6; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 8 | A7 | input | Data input to buffer/driver channel 7; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 9 | A8 | input | Data input to buffer/driver channel 8; inputs accept voltages up to 5.5 V and can be driven from 3.3-V or 5-V devices. |
| 10 | GND | power_in | Ground reference for the device; all unused inputs must be held at VCC or GND to ensure proper operation. |
| 11 | Y8 | tri_state | 3-state buffer output of channel 8; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 12 | Y7 | tri_state | 3-state buffer output of channel 7; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 13 | Y6 | tri_state | 3-state buffer output of channel 6; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 14 | Y5 | tri_state | 3-state buffer output of channel 5; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 15 | Y4 | tri_state | 3-state buffer output of channel 4; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 16 | Y3 | tri_state | 3-state buffer output of channel 3; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 17 | Y2 | tri_state | 3-state buffer output of channel 2; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 18 | Y1 | tri_state | 3-state buffer output of channel 1; high-impedance when OE1 or OE2 is high, and outputs are disabled without damaging backflow when the device is powered down (I_off). |
| 19 | OE2 | input | Active-low output enable for the second input of the 3-state AND gate; when OE2 or OE1 is high, all eight outputs are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to ensure high-impedance during power up or power down. |
| 20 | VCC | power_in | Supply voltage, operating range 2 V to 3.6 V (data retention down to 1.5 V), with 2.7 V to 3.6 V required for the stated VIH and VIL levels. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LVC541AQPWREP - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc541aqpwrep-etched.step/sn74lvc541aqpwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc541aqpwrep.step/sn74lvc541aqpwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
c27fb9eb0f32bcc1, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).