74LVC2G17GV,125

Nexperia Dual non-inverting Schmitt buffer; SOT457. Reusable component library under validation.

The symbol has separate channel and supply groups and a central manufacturer-derived chip outline. All six pin numbers and electrical types follow the manufacturer datasheet. Copper and paste follow the reflow drawing; +0.05 mm mask expansion is a provisional engineering choice. Pin-1 cues are present in fab and silk.

Manufacturer originals

• Datasheet
• Package and reflow lands
• Original STEP: Nexperia's SOT457 package page, download. Original bytes and hashes are retained in this repository.

Library inspection

• Grouped symbol
• Footprint layers

Canonical adom-lbr and KiCad files are in Files. Model pose/pin-1 seating, derived MPN marking, mask/process qualification and native KiCad/Fusion/Altium parity remain open. The supplied GLB is a conversion of the original STEP; neither rendered geometry nor successful import constitutes a completed PCB check.

Related projects

TMF8829 Depth Lab uses this component. Its circuit choices and project progress are documented there.

3D reference artwork

The derived display retains the source model geometry and materials, with a recorded rigid pose into Adom Z-up footprint coordinates. Nonphysical reference layers show teal dashed copper-pad boundaries at 50% opacity, silkscreen at 30% opacity, and signal names at 50% opacity. Labels follow the canonical pin-to-pad mapping. Unnamed nonpolarized passive connections are labeled “Terminal”; no polarity or signal function is invented. Original manufacturer STEP files remain unchanged.

Orbit underneath to compare contacts with copper boundaries. These are copper perimeters, not mask or paste apertures. Display artwork does not qualify native model seating, pin 1, electrical behavior or manufacture. The virtual MPN is applied through Adom Chip Laser at the chosen clear package surface described below. See 74LVC2G17GV,125.adom-reference-v3.overlay.json for source hashes, pose and layer metadata.

MPN marking, source and license

Mark location: Top cap, along long package axis and offset 0.45 mm toward the blank edge to avoid central manufacturer mark. The exact MPN is a virtual identification inlay generated by adom-chip-laser, not a claim about the manufacturer’s actual package marking. The physical source model and reference-artwork geometry remain unchanged.

The Source field links to the manufacturer/reference authority. Generation tools such as adom-lbr, adom-symbol, step2glb and Adom Chip Laser are recorded separately in artifact provenance. Original Adom-authored content defaults to the MIT open-source license; manufacturer and upstream assets retain their original terms and attribution. See license scope. Native CAD parity and manufacturing qualification are separate checks.

Cached chip artwork

These reusable chip previews and symbol outlines retain the reviewed Z-up pose and virtual MPN placement. Read the manifest before generating new artwork; compare its source hashes before reuse. Electrical and native model-seating qualification remain separate.

Cache manifest and generation recipe · Original manufacturer STEP

Component LODs

Four board-use detail levels preserve the reviewed Z-up pose and real package terminals. High and medium retain the virtual MPN in its reviewed location. All four exclude the footprint outlines, pad labels and silkscreen used by the separate annotated wiki hero; the EDA board supplies those layers.

Cached PNG/WebP previews show each level without starting another 3D viewer. Choose Turn on 3D preview to inspect zoom-driven detail changes. Closing or hiding that preview releases its models and viewer resources. The manifest records source hashes, geometry estimates and review limits; display fidelity does not establish native seating or manufacturing qualification.

LOD manifest and reuse contract