component

W5100S-L

Public Made by Adom

by adom

WIZNET Ethernet Transceivers, LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentinterfacew5100s-lfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

W5100S-L

WIZNET · Ethernet Transceivers · LQFP-48(7x7)

W5100S-L from WIZNET, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GNDA power_in Analog ground connection.
2 TXON output Differential transmitted signal pair (negative); differential data is transmitted to media via TXOP/TXON signal pair on MDI mode.
3 TXOP output Differential transmitted signal pair (positive); differential data is transmitted to media via TXOP/TXON signal pair on MDI mode.
4 1V2A power_in Analog 1.2V power; supplied from 1V20 voltage source.
5 RXIN input Differential received signal pair (negative); differential data is received from media via RXIP/RXIN signal pair on MDI mode.
6 RXIP input Differential received signal pair (positive); differential data is received from media via RXIP/RXIN signal pair on MDI mode.
7 GNDA power_in Analog ground connection.
8 3V3A power_in Analog 3.3V power.
9 RSET_BG output Off-chip bias resistor connection; must be connected to analog ground through external 12.3kΩ ±1% resistor.
10 GND power_in Digital ground connection.
11 XSCO output 25MHz clock output for crystal oscillator (TXAL) or external oscillator; used for internal clock stabilization.
12 XSCI input 25MHz clock input for crystal oscillator (TXAL) or external oscillator; used for internal clock stabilization.
13 1V2D power_in Digital 1.2V power; supplied from 1V20 voltage source.
14 1V2O power_out Internal regulator 1.2V power output with maximum 150mA capacity; must use ferrite bead filter and 3.3µF external capacitors.
15 3V3A power_in Analog 3.3V power.
16 GNDA power_in Analog ground connection.
17 LNKn output Link status LED output; low indicates link up, high indicates link down (valid in SPI and parallel bus modes).
18 SPDn output Link speed LED output; low indicates 100Mbps, high indicates 10Mbps (valid in SPI and parallel bus modes).
19 DPXn output Link duplex LED output; low indicates full-duplex, high indicates half-duplex (valid in SPI and parallel bus modes).
20 ACTn output Link activity LED output; flashes during link up with TX/RX, high during link down (valid in SPI and parallel bus modes).
21 COLn output Link collision detect LED output; low indicates collision detected, high indicates no collision (valid in SPI and parallel bus modes).
22 1V2D power_in Digital 1.2V power; supplied from 1V20 voltage source.
23 GND power_in Digital ground connection.
24 3V3D power_in Digital 3.3V power.
25 MOD[0] input Interface mode selection bit 0; modes: 0000=SPI, 010X=parallel bus; must be strapped before chip enable.
26 MOD[1] input Interface mode selection bit 1; modes: 0000=SPI, 010X=parallel bus; must be strapped before chip enable.
27 MOD[2] input Interface mode selection bit 2; modes: 0000=SPI, 010X=parallel bus; must be strapped before chip enable.
28 MOD[3] input Interface mode selection bit 3; modes: 0000=SPI, 010X=parallel bus; must be strapped before chip enable.
29 CSn input Chip select input with internal 75kΩ pull-up resistor; low selects W5100S, high deselects.
30 SCLK input SPI clock input in SPI mode; must be connected to GND or floated in parallel bus mode.
31 1V2D power_in Digital 1.2V power; supplied from 1V20 voltage source.
32 MOSI/ADDR0 input SPI master output slave input (data input) in SPI mode; address bit 0 in parallel bus mode.
33 MISO/ADDR1 bidirectional SPI master input slave output (data output) in SPI mode; address bit 1 in parallel bus mode.
34 RDn input Read strobe input with internal 75kΩ pull-up resistor in parallel bus mode; must be connected to 3V3D or floated in SPI mode.
35 WRn input Write strobe input with internal 75kΩ pull-up resistor in parallel bus mode indicating write operation.
36 3V3D power_in Digital 3.3V power.
37 DAT0 bidirectional 8-bit data bus bit 0; receives or transmits data from/to host in parallel bus mode; must be floated in SPI mode.
38 DAT1 bidirectional 8-bit data bus bit 1 with internal 75kΩ pull-down resistor; receives or transmits data in parallel bus mode; must be floated in SPI mode.
39 DAT2 bidirectional 8-bit data bus bit 2 with internal 75kΩ pull-down resistor; receives or transmits data in parallel bus mode; must be floated in SPI mode.
40 DAT3 bidirectional 8-bit data bus bit 3 with internal 75kΩ pull-down resistor; receives or transmits data in parallel bus mode; must be floated in SPI mode.
41 DAT4 bidirectional 8-bit data bus bit 4 with internal 75kΩ pull-down resistor; receives or transmits data in parallel bus mode; must be floated in SPI mode.
42 DAT5 bidirectional 8-bit data bus bit 5 with internal 75kΩ pull-down resistor; receives or transmits data in parallel bus mode; must be floated in SPI mode.
43 DAT6 bidirectional 8-bit data bus bit 6; receives or transmits data from/to host in parallel bus mode; must be floated in SPI mode.
44 DAT7 bidirectional 8-bit data bus bit 7; receives or transmits data from/to host in parallel bus mode; must be floated in SPI mode.
45 1V2D power_in Digital 1.2V power; supplied from 1V20 voltage source.
46 GND power_in Digital ground connection.
47 INTn output Interrupt output to host; low indicates interrupt occurred, high indicates no interrupt; polarity controlled via MR2[IEN].
48 RSTn input Reset input with internal pull-up resistor; must be asserted low for minimum 500ns; W5100S requires 60.3ms initialization after reset release.

Key specifications

Parameter Value
Manufacturer WIZNET
Package LQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: W5100S-L
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: w5100s-l-etched.step / w5100s-l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); w5100s-l.step / w5100s-l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WIZNET datasheet (109 pp, sha256 fca425bbdeeb7ace, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF