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CDCM61004RHBR

Public Made by Adom

by adom

Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-32-EP(5x5). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

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CDCM61004RHBR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-32-EP(5x5)

CDCM61004RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC_OUT power_in 3.3-V supply for the output buffers.
2 OUTN1 output Differential output N for pair 1; part of OUTP1/OUTN1 differential output pair or two single-ended outputs.
3 OUTP1 output Differential output P for pair 1; part of OUTP1/OUTN1 differential output pair or two single-ended outputs.
4 VCC_OUT power_in 3.3-V supply for the output buffers.
5 OUTN0 output Differential output N for pair 0; part of OUTP0/OUTN0 differential output pair or two single-ended outputs.
6 OUTP0 output Differential output P for pair 0; part of OUTP0/OUTN0 differential output pair or two single-ended outputs.
7 CE input Chip enable control pin with internal pullup resistor; see Table 8 for configuration.
8 NC unconnected No connection.
9 VCC_VCO power_in 3.3-V supply for the internal VCO.
10 OS1 input Output type select control pin with internal pullup resistor; part of OS1/OS0 pair, see Table 7 for output type configuration.
11 OS0 input Output type select control pin with internal pullup resistor; part of OS1/OS0 pair, see Table 7 for output type configuration.
12 RSTN input Device reset pin with internal pullup resistor; active low to initiate PLL recalibration when settings change.
13 OD2 input Output divider control pin with internal pullup resistor; part of OD2/OD1/OD0 triple, see Table 6 for divider selection.
14 OD1 input Output divider control pin with internal pullup resistor; part of OD2/OD1/OD0 triple, see Table 6 for divider selection.
15 OD0 input Output divider control pin with internal pullup resistor; part of OD2/OD1/OD0 triple, see Table 6 for divider selection.
16 VCC_PLL2 power_in 3.3-V supply for the PLL circuitry.
17 REG_CAP2 passive Capacitor connection for internal regulator; connect to a 10-μF Y5V capacitor to GND.
18 VCC_PLL1 power_in 3.3-V supply for the PLL circuitry.
19 REG_CAP1 passive Capacitor connection for internal regulator; connect to a 10-μF Y5V capacitor to GND.
20 VCC_IN power_in 3.3-V supply for the input buffers.
21 XIN input Crystal or LVCMOS reference input accepting parallel resonant crystal or LVCMOS inputs in the range 21.875 MHz to 28.47 MHz.
22 GND1 power_in Additional ground for device; GND1 shorted on-chip to ground.
23 OSC_OUT output Bypass LVCMOS output clock.
24 NC unconnected No connection.
25 PR0 input Prescaler and feedback divider control pin with internal pullup resistor; part of PR0/PR1 pair, see Table 5 for configuration.
26 PR1 input Prescaler and feedback divider control pin with internal pullup resistor; part of PR0/PR1 pair, see Table 5 for configuration.
27 VCC_OUT power_in 3.3-V supply for the output buffers.
28 OUTN3 output Differential output N for pair 3; part of OUTP3/OUTN3 differential output pair or two single-ended outputs.
29 OUTP3 output Differential output P for pair 3; part of OUTP3/OUTN3 differential output pair or two single-ended outputs.
30 VCC_OUT power_in 3.3-V supply for the output buffers.
31 OUTN2 output Differential output N for pair 2; part of OUTP2/OUTN2 differential output pair or two single-ended outputs.
32 OUTP2 output Differential output P for pair 2; part of OUTP2/OUTN2 differential output pair or two single-ended outputs.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Supply voltage VCC -0.5 4.6 V All supply voltages must be supplied simultaneously 7
Input voltage (max printed as VCC_IN + 0.5) VIN -0.5 V 7
Output voltage range (max printed as VCC_OUT + 0.5) VOUT -0.5 V 7
Input current IIN -20 20 mA 7
Output current IOUT -50 50 mA 7
Storage temperature Tstg -65 150 °C 7
Output supply voltage VCC_OUT 3 3.3 3.6 V 7
PLL supply voltage (VCC_PLL1) VCC_PLL1 3 3.3 3.6 V 7
PLL supply voltage (VCC_PLL2) VCC_PLL2 3 3.3 3.6 V 7
On-chip VCO supply voltage VCC_VCO 3 3.3 3.6 V 7
Input supply voltage VCC_IN 3 3.3 3.6 V 7
Ambient temperature TA -40 85 °C 7
Allowable temperature drift for continuous PLL lock (column position not recoverable from text) /TCL/ 100 °C 7
Input high voltage (printed as 0.6 VCC) VIH 0.6 VCC 9
Input low voltage (printed as 0.4 VCC) VIL 0.4 VCC 9
Input high current (column position inferred from single value) IIH 200 μA VCC = 3.6 V, VIL = 0 V 9
Input low current (column position inferred from single value) IIL -200 μA VCC = 3 V, VIH = 3.6 V 9
Bypass output frequency (LVCMOS) fOSC_OUT 21.875 28.47 MHz 9
Output frequency (LVCMOS) fOUT 43.75 250 MHz 9
Output high voltage (LVCMOS; printed as VCC -0.5 V) VOH -0.5 V VCC = min to max, IOH = -100 μA 9
Output low voltage (LVCMOS) VOL 0.3 V VCC = min to max, IOL = 100 μA 9
RMS phase jitter (LVCMOS) tRJIT 0.85 ps, RMS 250 MHz (10 kHz to 20 MHz) 9
Output rise/fall slew rate (LVCMOS) tSLEW-RATE 2.4 V/ns 20% to 80% 9
Output duty cycle (LVCMOS) ODC 45 55 % 9
Skew between outputs (LVCMOS) tSKEW 60 ps 9
Device current, LVCMOS ICC 175 205 mA fIN = 25 MHz, fOUT = 250 MHz, CL = 5 pF 9
Output frequency (LVPECL) fOUT 43.75 683.264 MHz 9
Output high voltage (LVPECL; printed as VCC -1.18 / VCC -0.73) VOH -1.18 -0.73 V 9
Output low voltage (LVPECL; printed as VCC -2 / VCC -1.55) VOL -2 -1.55 V 9
Differential output voltage (LVPECL) /VOD/ 0.6 1.23 V 9
RMS phase jitter (LVPECL) tRJIT 0.77 ps, RMS 625 MHz (10 kHz to 20 MHz) 9
Output rise/fall time (LVPECL) tR/tF 175 ps 20% to 80% 9
Output duty cycle (LVPECL) ODC 45 55 % 9
Skew between outputs (LVPECL) tSKEW 30 ps 9
Device current, LVPECL ICC 180 215 mA fIN = 25 MHz, fOUT = 625 MHz 9
Output frequency (LVDS) fOUT 43.75 683.264 MHz 9
Differential output voltage (LVDS) /VOD/ 0.247 0.454 V 9
VDD magnitude change ΔVOD 50 mV 9
Common-mode voltage (LVDS) VOS 1.125 1.375 V 9
VOS magnitude change ΔVOS 50 mV 9
RMS phase jitter (LVDS) tRJIT 0.73 ps, RMS 625 MHz (10 kHz to 20 MHz) 9
Output rise/fall time (LVDS) tR/tF 255 ps 20% to 80% 9
Output duty cycle (LVDS) ODC 45 55 % 9
Skew between outputs (LVDS) tSKEW 40 ps 9
Device current, LVDS ICC 150 195 mA fIN = 25 MHz, fOUT = 625 MHz 9
Crystal frequency 21.875 28.47 MHz 11
Equivalent series resistance (ESR; column position inferred from single value) ESR 50 Ω 11
On-chip load capacitance 8 10 pF 11
Drive level 0.1 1 mW 11
Maximum shunt capacitance C0 7 pF 11
Input capacitance CIN 10 pF 6
Input pullup resistor RPULLUP 150 kΩ 6
Junction-to-ambient thermal resistance RθJA 33.1 °C/W 8
Junction-to-case (top) thermal resistance RθJC(top) 25.7 °C/W 8
Junction-to-board thermal resistance RθJB 0.3 °C/W 8
Junction-to-top characterization parameter ψJT 7.1 °C/W 8
Junction-to-board characterization parameter ψJB 2 °C/W 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 6.12 °C/W 8
Thermal resistance, junction-to-ambient (dissipation rating) θJA 35 °C/W 0 LFM; 4 × 4 vias on pad 11
Thermal resistance, junction-to-pad θJP 4 °C/W 11

CAD (KiCad official)

  • Symbol: CDCM61004RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: cdcm61004rhbr-etched.step / cdcm61004rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcm61004rhbr.step / cdcm61004rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 c6638756c414d47b, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF