component
TLV7113030DDSER
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6(1.5x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV7113030DDSER
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6(1.5x1.5)
TLV7113030DDSER from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN1 | input | Enable pin for regulator 1: driving EN1 over 0.9V turns on regulator 1, and driving it below 0.4V puts regulator 1 into shutdown mode. |
| 2 | IN | power_in | Input pin; a small capacitor is needed from this pin to ground to assure stability (see Input and Output Capacitor Requirements). |
| 3 | EN2 | input | Enable pin for regulator 2: driving EN2 over 0.9V turns on regulator 2, and driving it below 0.4V puts regulator 2 into shutdown mode. |
| 4 | GND | power_in | Ground pin. |
| 5 | OUT2 | power_out | Regulated output voltage pin for channel 2; a small 1μF ceramic capacitor is needed from this pin to ground to assure stability. |
| 6 | OUT1 | power_out | Regulated output voltage pin for channel 1; a small 1μF ceramic capacitor is needed from this pin to ground to assure stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2 | 5.5 | V | 3 | ||
| Output voltage range | VO | 1.2 | 4.8 | V | 3 | ||
| DC output accuracy | VOUT | -2 | 2 | % | -40°C ≤ TJ ≤ +125°C | 3 | |
| Line regulation | ΔVO/ΔVIN | 1 | 5 | mV | VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V | 3 | |
| Load regulation | ΔVO/ΔIOUT | 5 | 15 | mV | 0mA ≤ IOUT ≤ 200mA | 3 | |
| Dropout voltage | VDO | 150 | 215 | mV | VIN = 0.98V × VOUT(NOM), IOUT = 200mA, 2.8V ≤ VOUT < 3.3V | 3 | |
| Output current limit | ICL | 220 | 350 | 550 | mA | VOUT = 0.9 × VOUT(NOM) | 3 |
| Quiescent current (both enabled) | IQ | 70 | 110 | µA | VEN1 = high, VEN2 = high, IOUT = 0mA | 3 | |
| Shutdown current | ISHUTDOWN | 2.5 | 4 | μA | VEN1,2 ≤ 0.4V, 2.0V ≤ VIN ≤ 4.5V | 3 | |
| Enable high (enabled) threshold | VHI | 0.9 | V | Enable high (enabled); printed as 0.9 VIN | 3 | ||
| Enable low (shutdown) threshold | VLO | 0 | 0.4 | V | Enable low (shutdown) | 3 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| Input voltage | IN | -0.3 | 6 | V | All voltages with respect to ground | 2 | |
| Enable voltage | EN | -0.3 | V | Maximum printed as VIN + 0.3 | 2 | ||
| Output voltage | OUT | -0.3 | 6 | V | All voltages with respect to ground | 2 | |
| Operating junction temperature (absolute maximum) | TJ | -55 | 150 | °C | At TJ = –40°C to +125°C (unless otherwise noted) | 2 | |
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Electrostatic discharge, human body model | 2 | kV | HBM, QSS 009-105 (JESD22-A114A) | 2 | |||
| Electrostatic discharge, charged device model | 500 | V | CDM, QSS 009-147 (JESD22-C101B.01) | 2 | |||
| Junction-to-top characterization parameter | ψJT | 6 | °C/W | DSE package, 6 pins | 2 | ||
| Junction-to-ambient thermal resistance (EVM) | RθJA | 170 | °C/W | DSE package, 2-layer EVM board, per Table 1 | 19 | ||
| Output capacitor ESR | ESR | 200 | mΩ | COUT requirement in application information | 18 | ||
| Output capacitor effective capacitance | COUT | 0.1 | µF | Effective capacitance under operating bias voltage and temperature | 18 |
CAD (KiCad official)
- Symbol:
TLV7113030DDSER - Footprint:
Package_SON:WSON-6_1.5x1.5mm_P0.5mm - 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files:
tlv7113030ddser-etched.step/tlv7113030ddser-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv7113030ddser.step/tlv7113030ddser.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
c031b3f1063a02c1, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).