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Contents

README

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CA-IF1033S

Chipanalog · CAN Transceivers · SOIC-8

CA-IF1033S from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input: driving TXD high makes the bus recessive and driving it low makes the bus dominant, with an internal pull-up to VCC.
2 GND power_in Power ground for the device.
3 VCC power_in Supply input (recommended 3 V to 3.6 V, absolute maximum 7 V); place a 0.1 µF capacitor between VCC and GND as close to the device as possible.
4 RXD output Receiver output: high when CANH and CANL are recessive and low when they are dominant, with recommended output current limited to ±2 mA and absolute maximum 8 mA.
5 SHDN input Shutdown input: low enables the driver and receiver, high shuts the device down, and the pin has an internal pull-down to GND.
6 CANL bidirectional Low-level CAN bus line; bus pins withstand ±18 V and bus-pin ESD protection exceeds ±25 kV HBM.
7 CANH bidirectional High-level CAN bus line; bus pins withstand ±18 V and bus-pin ESD protection exceeds ±25 kV HBM.
8 STB input Mode select input: high selects low-power standby mode with remote wake-up, low selects normal mode, and the pin has an internal pull-down to GND.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC bus supply voltage (absolute maximum) VCC -0.3 7 V 5
CAN bus IO voltage (CANH, CANL) V(BUS) -18 18 V 5
Maximum differential voltage CANH to CANL V(DIFF) -18 18 V 5
Logic-side input voltage (TXD, S, STB, EN, SHDN) V(Logic_Input) -0.3 V 5
Logic-side output voltage (RXD) V(Logic_Output) -0.3 V 5
Logic-side output current (RXD) IO(Logic_Output) 8 mA 5
Junction temperature TJ -55 150 °C 5
Storage temperature TSTG -65 150 °C 5
CAN bus supply voltage (recommended) VCC 3 3.6 V 5
RXD pin high-level output current IOH(RXD) -2 mA 5
RXD pin low-level output current IOL(RXD) 2 mA 5
Operating ambient temperature range TA -40 125 °C 5
Supply current, normal mode, typical bus load Icc 40 55 mA TXD=0V, RL=60 Ohm, CL=open, RCM=open, S/STB/SHDN=0V, EN=VCC, typical bus load 6
Supply current, normal mode, high bus load Icc 44 60 mA TXD=0V, RL=50 Ohm, CL=open, RCM=open, S/STB/SHDN=0V, EN=VCC, high bus load 6
Supply current, dominant with CANH at -12V Icc 110 180 mA TXD=0V, S/STB/SHDN=0V, CANH=-12V, RL=open, CL=open, RCM=open, EN=VCC 6
Supply current, recessive (TXD high) Icc 0.9 2 mA TXD=VCC, RL=50 Ohm, RCM=open, CL=open, S/STB/SHDN=0V, EN=VCC 6
Supply current, standby mode (CA-IF1033S) Icc 9 15 μA TXD=VCC, RL=50 Ohm, RCM=open, CL=open, STB=VCC, SHDN=0V 6
Supply current, shutdown mode (CA-IF1033S) Icc 1 μA TXD=VCC, RL=50 Ohm, RCM=open, CL=open, SHDN=VCC / EN=0V 6
VCC UVLO rising threshold UVVCC+ 2.2 2.6 V 6
VCC UVLO falling threshold UVVCC- 1.65 2 2.5 V 6
High-level input voltage (S, STB, SHDN, EN) VIH 2 V 6
Low-level input voltage (S, STB, SHDN, EN) VIL 0.8 V 6
High-level input leakage current (S, STB, SHDN, EN) IIH -3 10 μA 6
Low-level input leakage current (S, STB, SHDN, EN) IIL -4 1 μA 6
Unpowered leakage current (S, STB, SHDN, EN) Ilek(off) -3 5 μA 6
High-level input voltage (TXD) VIH 2 V 6
Low-level input voltage (TXD) VIL 0.8 V 6
High-level input leakage current (TXD) IIH -2.5 0 3 μA TXD=VCC=3.6V 6
Low-level input leakage current (TXD) IIL -4 0 μA TXD=0V, VCC=3.6V 6
Unpowered leakage current (TXD) Ilek(off) -2 0 2.5 μA TXD=3.6V, VCC=0V 6
Low-level output voltage (RXD) VOL 0.2 0.4 V Io=2mA 6
Unpowered leakage current (RXD) Ilek(off) -1 0 1 μA RXD=3.6V, VCC=0V 6
Single-ended dominant output voltage, CANH VO(DOM) 2.45 V Normal mode, TXD=0V, RL=60 Ohm, CL=open, RCM=open, CANH pin 6
Single-ended dominant output voltage, CANL VO(DOM) 0.5 1.25 V Normal mode, TXD=0V, RL=50-65 Ohm, CL=open, RCM=open, CANL pin 6
Standby bus voltage, CANH VO(STB) -0.1 0.1 V Standby mode 3, RL open, RCM open, CANH 7
Standby bus voltage, CANL VO(STB) -0.1 0.1 V Standby mode 3, RL open, RCM open, CANL 7
Standby differential bus voltage, CANH-CANL VO(STB) -0.2 0.2 V Standby mode 3, RL open, RCM open, CANH-CANL 7
Differential output voltage, dominant (RL 45-50 Ohm) VOD(DOM) 1.5 2 3 V Normal mode, TXD=0V, RL=45-50 Ohm, RCM open, CANH-CANL 7
Differential output voltage, dominant (RL 50-65 Ohm) VOD(DOM) 1.6 3 V Normal mode, TXD=0V, RL=50-65 Ohm, RCM open, CANH-CANL 7
Differential output voltage, recessive (RL 60 Ohm) VOD(REC) -120 12 mV Normal mode, TXD=VCC, RL=60 Ohm, CL=open, RCM=open, CANH-CANL 7
Differential output voltage, recessive (RL open) VOD(REC) -50 50 mV Normal mode, TXD=VCC, RL=open, CL=open, RCM=open, CANH-CANL 7
DC symmetry (dominant and recessive) Vsym_DC -0.4 0.4 V Normal mode, RL=60 Ohm, RCM open 7
Short-circuit current, dominant (CANH at -12V) IOS(SS_DOM) -200 mA Normal mode, TXD=0V, CANL open, CANH=-12V 7
Short-circuit current, dominant (CANL at 12V) IOS(SS_DOM) 200 mA Normal mode, TXD=0V, CANH open, CANL=12V 7
Short-circuit current, recessive IOS(SS_rec) -5 5 mA Normal mode, TXD=VCC, VBUS=CANH=CANL from -12V to 12V 7
Common-mode input voltage range VCM -12 12 V Normal mode, listen mode and standby mode, RXD output valid 7
Normal/listen mode input threshold voltage VIT 500 900 mV Normal and listen mode, Vcm from -12V to 12V 7
Standby mode input threshold voltage VIT(STB) 400 1150 mV Standby mode 3, Vcm from -12V to 12V 7
CANH/CANL input resistance RIN 10 40 kΩ Normal mode, TXD=VCC 7
Differential input resistance RDIFF 20 80 kΩ Normal mode, TXD=VCC 7
Input resistance matching RDIFF(M) -3 3 % CANH=CANL 7
Input leakage current ILKG 5 μA VCC=0V, VCANH=VCANL=3.3V 7
Dominant timeout (TXD) tDTO 1.6 3 5 ms Normal mode, RL=60 Ohm, CL open, Fig 7-5 8
Loop delay, recessive to dominant tloop1 105 255 ns RL=60 Ohm, CL=100pF, Fig 7-3 8
Loop delay, dominant to recessive tloop2 130 255 ns RL=60 Ohm, CL=100pF, Fig 7-3 8
Mode transition time (standby to normal or normal to standby) TMODE 12 45 μs Fig 7-4 8
Valid wake-up filter time tWK_FILTER 0.5 1.8 μs Fig 9-4 8
Bus wake-up timeout tWK_TIMEOUT 0.8 10 ms Fig 9-4 8
Thermal resistance junction-to-ambient (SOIC8) RθJA 170 °C/W SOIC8 package column 5
Thermal shutdown threshold TTSD1 170 °C 7

CAD (KiCad official)

  • Symbol: CA-IF1033S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ca-if1033s-etched.step / ca-if1033s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-if1033s.step / ca-if1033s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (24 pp, sha256 cf1740e1bc106780, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF