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NVT2010BS
Public Made by Adomby adom
NXP Semicon Translators / Level Shifters, HVQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNVT2010BS
NXP Semicon · Translators / Level Shifters · HVQFN-24-EP(4x4)
NVT2010BS from NXP Semicon, in a HVQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A2 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 2 | A3 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 3 | A4 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 4 | A5 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 5 | A6 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 6 | A7 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 7 | A8 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 8 | A9 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 9 | A10 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 10 | B10 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 11 | B9 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 12 | B8 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 13 | B7 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 14 | B6 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 15 | B5 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 16 | B4 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 17 | B3 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 18 | B2 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 19 | B1 | bidirectional | High-voltage side I/O; connect to VREFB through a pull-up resistor. |
| 20 | VREFB | power_in | High-voltage side reference supply voltage for Bn (Vref(B) 1.8 V to 5.5 V per the general description). |
| 21 | EN | input | Switch enable input; connect to VREFB and pull-up through a high resistor, and it must be LOW during power-up or power-down to keep the An and Bn pins high-impedance. |
| 22 | GND | power_in | Ground (0 V). |
| 23 | VREFA | power_in | Low-voltage side reference supply voltage for An (Vref(A) 1.0 V to 3.6 V per the general description). |
| 24 | A1 | bidirectional | Low-voltage side I/O; connect to VREFA through a pull-up resistor. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | HVQFN-24-EP(4x4) |
| Category | Logic ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VI/O voltage on an input/output pin | VI/O | 0 | 5.5 | V | An, Bn | 13 | |
| reference voltage (A) | Vref(A) | 0 | 5.4 | V | VREFA | 13 | |
| reference voltage (B) | Vref(B) | 0 | 5.5 | V | VREFB | 13 | |
| input voltage on pin EN | VI(EN) | 0 | 5.5 | V | 13 | ||
| pass switch current | Isw(pass) | 64 | mA | 13 | |||
| ambient temperature | Tamb | -40 | 85 | °C | operating in free-air | 13 | |
| reference voltage (A) | Vref(A) | -0.5 | 6 | V | 12 | ||
| reference voltage (B) | Vref(B) | -0.5 | 6 | V | 12 | ||
| input voltage | VI | -0.5 | 6 | V | 12 | ||
| voltage on an input/output pin | VI/O | -0.5 | 6 | V | 12 | ||
| channel current (DC) | Ich | 128 | mA | 12 | |||
| input clamping current | IIK | -50 | mA | VI <0V | 12 | ||
| output clamping current | IOK | -50 | 50 | mA | 12 | ||
| storage temperature | Tstg | -65 | 150 | °C | 12 | ||
| input clamping voltage | VIK | 1.2 | V | II = 18 mA; VI(EN) =0V | 13 | ||
| HIGH-level input current | IIH | 5 | µA | VI = 5 V; VI(EN) =0V | 13 | ||
| off-state input/output capacitance | Cio(off) | 5 | 6 | pF | An, Bn; VO = 3 V or 0 V; VI(EN) =0V | 13 | |
| on-state input/output capacitance | Cio(on) | 11.5 | 13 | pF | An, Bn; VO = 3 V or 0 V; VI(EN) =3V | 13 | |
| ON-state resistance | Ron | 1 | 2.7 | 5 | Ω | An, Bn; VI = 0 V; IO = 64 mA; VI(EN) = 4.5 V | 13 |
| ON-state resistance | Ron | 4.8 | 7.5 | Ω | VI = 2.4 V; IO = 15 mA; VI(EN) = 4.5 V | 13 | |
| reference voltage (B) | Vref(B) | 2.1 | 5 | V | 7 | ||
| input voltage on pin EN | VI(EN) | 2.1 | 5 | V | 7 | ||
| reference voltage (A) | Vref(A) | 0 | 1.5 | 4.4 | V | 7 |
CAD (KiCad official)
- Symbol:
NVT2010BS - Footprint:
Package_DFN_QFN:HVQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm - 3D model: HVQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
nvt2010bs-etched.step/nvt2010bs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nvt2010bs.step/nvt2010bs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NXP Semicon datasheet (33 pp, sha256
3c08396afa780245, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).