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Contents

README

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SIA906EDJ-T1-GE3

Vishay Intertech · MOSFETs · WSON-6-EP(2x2)

SIA906EDJ-T1-GE3 from Vishay Intertech, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (N-channel, VDS 20 V, VGS ±12 V max).
2 G1 input Gate of MOSFET 1 (VGS ±12 V max, VGS(th) 0.6 to 1.4 V).
3 D2 passive Drain of MOSFET 2, connected to the D2 exposed die pad (VDS 20 V max, ID 4.5 A package limited).
4 S2 passive Source of MOSFET 2 (N-channel, VDS 20 V, VGS ±12 V max).
5 G2 input Gate of MOSFET 2 (VGS ±12 V max, VGS(th) 0.6 to 1.4 V).
6 D1 passive Drain of MOSFET 1, connected to the D1 exposed die pad (VDS 20 V max, ID 4.5 A package limited).
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package WSON-6-EP(2x2)
Category Transistors/Thyristors
Pins 7

CAD (KiCad official)

  • Symbol: SIA906EDJ-T1-GE3
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: sia906edj-t1-ge3-etched.step / sia906edj-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sia906edj-t1-ge3.step / sia906edj-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 47a00dc872650cf7, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF