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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LMX2572LPRHAT

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · HVQFN-40-EP(6x6)

LMX2572LPRHAT from Texas Instruments, in a HVQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CE	input	Chip enable: high-impedance CMOS input for 1.8-V to 3.3-V logic; active HIGH powers on the device.
2	GND	power_in	VCO ground.
3	VbiasVCO	passive	Bypass VCO bias; connect a 470-nF (X7R) decoupling capacitor to VCO ground as close to this pin as possible.
4	GND	power_in	VCO ground.
5	SYNC	input	Phase synchronization trigger; configurable to accept CMOS input (1.8-V to 3.3-V logic) or differential input.
6	GND	power_in	Digital ground.
7	VccDIG	power_in	Digital power supply; connect a 0.1-µF decoupling capacitor to digital ground.
8	OSCinP	input	Reference input clock (+); high-impedance self-biasing pin that requires AC-coupling.
9	OSCinM	input	Reference input clock (-); high-impedance self-biasing pin that requires AC-coupling.
10	VregIN	passive	Input reference path regulator output; connect a 1-µF decoupling capacitor to RF ground as close to this pin as possible.
11	VccCP	power_in	Supply for charge pump; connect a 0.1-µF decoupling capacitor to charge pump ground.
12	CPout	output	Charge pump output; place C1 of the loop filter close to this pin.
13	GND	power_in	Charge pump ground.
14	GND	power_in	Digital ground.
15	VccMASH	power_in	Digital power supply; connect a 1-µF decoupling capacitor to digital ground.
16	SCK	input	SPI clock: high-impedance CMOS input for 1.8-V to 3.3-V logic.
17	SDI	input	SPI data: high-impedance CMOS input for 1.8-V to 3.3-V logic.
18	RFoutBM	output	Differential output B (-): low-impedance output that requires AC-coupling.
19	RFoutBP	output	Differential output B (+): low-impedance output that requires AC-coupling.
20	MUXout	output	Multiplexed output configurable between lock detect and register readback.
21	VccBUF	power_in	Supply for output buffers; connect a 0.1-µF decoupling capacitor to RF ground.
22	RFoutAM	output	Differential output A (-): low-impedance output that requires AC-coupling.
23	RFoutAP	output	Differential output A (+): low-impedance output that requires AC-coupling.
24	CSB	input	SPI latch: high-impedance CMOS input for 1.8-V to 3.3-V logic.
25	GND	power_in	VCO ground.
26	VccVCO2	power_in	Supply for VCO; connect a 1-µF decoupling capacitor to VCO ground.
27	VbiasVCO2	passive	Bypass VCO bias; connect a 100-nF (X7R) decoupling capacitor to VCO ground.
28	SysRefReq	input	FSK I2S frame sync input: high-impedance CMOS input for 1.8-V to 3.3-V logic.
29	VrefVCO2	passive	Bypass VCO supply reference; connect a 10-µF decoupling capacitor to VCO ground.
30	RampClk	input	Ramp trigger in automatic ramping mode or ramp clock in manual ramping mode; can also serve as FSK I2S clock input; high-impedance CMOS input for 1.8-V to 3.3-V logic.
31	GND	power_in	VCO ground.
32	RampDir	input	Ramp trigger in automatic ramping mode or ramp segment selection in manual ramping mode; can also serve as FSK I2S data input; high-impedance CMOS input for 1.8-V to 3.3-V logic.
33	VbiasVARAC	passive	Bypass VCO varactor bias; connect a 10-µF decoupling capacitor to VCO ground.
34	GND	power_in	VCO ground.
35	Vtune	input	VCO tuning voltage input; connect a 1.5-nF or larger capacitor to VCO ground (see External Loop Filter).
36	VrefVCO	passive	Bypass VCO supply reference; connect a 10-µF decoupling capacitor to VCO ground.
37	VccVCO	power_in	Supply for VCO; connect a 1-µF decoupling capacitor to VCO ground.
38	VregVCO	passive	Bypass VCO regulator node; connect a 10-nF decoupling capacitor to VCO ground.
39	GND	power_in	VCO ground.
40	GND	power_in	Digital ground.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HVQFN-40-EP(6x6)
Category	RTC/Clock Chip
Pins	41

CAD (KiCad official)

Symbol: LMX2572LPRHAT
Footprint: Package_DFN_QFN:HVQFN-40-1EP_6x6mm_P0.5mm_EP4.1x4.1mm
3D model: HVQFN-40-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: lmx2572lprhat-etched.step / lmx2572lprhat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmx2572lprhat.step / lmx2572lprhat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (87 pp, sha256 69f0bb4362d891e6, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF