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ATSAM3U4EA-AU

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified ATSAM3U4EA-AU

by Ray · last 30 Oct 2026 · 1 record · files match
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30 Oct 2026RayPublished by the parts factory: tier mfr, 144 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAM3U4EA-AU · LQFP-144(20x20) · 144 pins
  • ✓copper: 144 copper pads, none touching another net
  • ✓datasheet: all 144 pin names found in the 1163-page datasheet
  • ✓distributor: lcsc C916225, digikey ATSAM3U4EA-AU-ND, mouser 556-ATSAM3U4EA-AU
  • ✓family: LQFP-144_20x20mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-mgnphqit/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 144 pins = 144 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 144 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
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Contents

README

markdown

ATSAM3U4EA-AU

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-144(20x20)

ATSAM3U4EA-AU from Microchip Tech, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TDI input JTAG test data input, used in JTAG debug and boundary-scan operation.
2 VDDOUT power_out Output of the on-chip voltage regulator.
3 VDDIN power_in Powers the voltage regulator.
4 TDO/TRACESWO output JTAG test data output, shared with asynchronous trace output TRACESWO in SWD mode; the pin is in input mode outside debug, so an external 100 kΩ pull-up is required to avoid floating-input current.
5 PB31 bidirectional PIO Controller B line 31; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
6 PB30 bidirectional PIO Controller B line 30; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
7 TMS/SWDIO bidirectional JTAG test mode select, or serial wire data input/output in SWD mode.
8 PB29 bidirectional PIO Controller B line 29; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
9 TCK/SWCLK input JTAG test clock, or serial wire clock in SWD mode.
10 PB28 bidirectional PIO Controller B line 28; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
11 NRST bidirectional Microcontroller reset, active low, configured as input/output.
12 PB27 bidirectional PIO Controller B line 27; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
13 PB26 bidirectional PIO Controller B line 26; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
14 PB25 bidirectional PIO Controller B line 25; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
15 PB24 bidirectional PIO Controller B line 24; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
16 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
17 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
18 GND power_in Ground common to the VDDCORE and VDDIO supplies.
19 PB23 bidirectional PIO Controller B line 23; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
20 PB22 bidirectional PIO Controller B line 22; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
21 PB21 bidirectional PIO Controller B line 21; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
22 PC21 bidirectional PIO Controller C line 21; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
23 PB20 bidirectional PIO Controller B line 20; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
24 PB19 bidirectional PIO Controller B line 19; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
25 PB18 bidirectional PIO Controller B line 18; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
26 PB17 bidirectional PIO Controller B line 17; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
27 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
28 PC14 bidirectional PIO Controller C line 14; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
29 PB14 bidirectional PIO Controller B line 14; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
30 PB10 bidirectional PIO Controller B line 10; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
31 PB9 bidirectional PIO Controller B line 9; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
32 PC19 bidirectional PIO Controller C line 19; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
33 GNDPLL power_in Separate ground for VDDPLL, which powers PLL A, UPLL and the 3-20 MHz oscillator.
34 VDDPLL power_in Powers PLL A, UPLL and the 3-20 MHz oscillator; voltage range 1.62-1.95 V.
35 XOUT output Output of the 3-20 MHz crystal oscillator.
36 XIN input Input of the 3-20 MHz crystal oscillator, powered by VDDPLL.
37 DHSDP bidirectional Positive data line of the High Speed USB Device Port, which has an embedded transceiver.
38 DHSDM bidirectional Negative data line of the High Speed USB Device Port, which has an embedded transceiver.
39 VBG passive Bandgap voltage node listed in the pinout; the provided text gives no electrical description for this pin.
40 VDDUTMI power_in Powers the UTMI+ interface; voltage range 3.0-3.6 V, 3.3 V nominal.
41 DFSDM bidirectional USB data line (negative) listed in the pinout; the provided text gives no electrical description for this pin.
42 DFSDP bidirectional USB data line (positive) listed in the pinout; the provided text gives no electrical description for this pin.
43 GNDUTMI power_in Separate ground for VDDUTMI, which powers the UTMI+ interface.
44 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
45 PA28 bidirectional PIO Controller A line 28; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
46 PA29 bidirectional PIO Controller A line 29; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
47 PC22 bidirectional PIO Controller C line 22; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
48 PA31 bidirectional PIO Controller A line 31; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
49 PC23 bidirectional PIO Controller C line 23; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
50 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
51 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
52 GND power_in Ground common to the VDDCORE and VDDIO supplies.
53 PB0 bidirectional PIO Controller B line 0; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
54 PC24 bidirectional PIO Controller C line 24; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
55 PB1 bidirectional PIO Controller B line 1; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
56 PC25 bidirectional PIO Controller C line 25; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
57 PB2 bidirectional PIO Controller B line 2; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
58 PC26 bidirectional PIO Controller C line 26; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
59 PB11 bidirectional PIO Controller B line 11; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
60 GND power_in Ground common to the VDDCORE and VDDIO supplies.
61 PB12 bidirectional PIO Controller B line 12; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
62 PB13 bidirectional PIO Controller B line 13; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
63 PC27 bidirectional PIO Controller C line 27; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
64 PA27 bidirectional PIO Controller A line 27; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
65 PB5 bidirectional PIO Controller B line 5; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
66 PB6 bidirectional PIO Controller B line 6; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
67 PB7 bidirectional PIO Controller B line 7; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
68 PB8 bidirectional PIO Controller B line 8; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
69 PC28 bidirectional PIO Controller C line 28; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
70 PC29 bidirectional PIO Controller C line 29; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
71 PC30 bidirectional PIO Controller C line 30; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
72 PC31 bidirectional PIO Controller C line 31; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
73 VDDANA power_in Powers the ADC cells; voltage range 2.0-3.6 V.
74 ADVREF input Reference voltage for the 10-bit ADC; conversions extend from 0 V to ADVREF.
75 GNDANA power_in Separate ground for VDDANA, which powers the ADC cells.
76 AD12BVREF input Reference voltage for the 12-bit ADC; conversions extend from 0 V to AD12BVREF.
77 PA22/PGMD14 bidirectional PIO Controller A line 22, with alternate parallel-programming function PGMD14 (see Section 21, FFPI).
78 PA30 bidirectional PIO Controller A line 30; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
79 PB3 bidirectional PIO Controller B line 3; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
80 PB4 bidirectional PIO Controller B line 4; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
81 PC15 bidirectional PIO Controller C line 15; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
82 PC16 bidirectional PIO Controller C line 16; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
83 PC17 bidirectional PIO Controller C line 17; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
84 PC18 bidirectional PIO Controller C line 18; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
85 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
86 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
87 PA13/PGMD5 bidirectional PIO Controller A line 13, with alternate parallel-programming function PGMD5 (see Section 21, FFPI); also SPI MISO per Table 31-2.
88 PA14/PGMD6 bidirectional PIO Controller A line 14, with alternate parallel-programming function PGMD6 (see Section 21, FFPI); also SPI MOSI per Table 31-2.
89 PC10 bidirectional PIO Controller C line 10; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
90 GND power_in Ground common to the VDDCORE and VDDIO supplies.
91 PA15/PGMD7 bidirectional PIO Controller A line 15, with alternate parallel-programming function PGMD7 (see Section 21, FFPI); also SPI SPCK per Table 31-2.
92 PC11 bidirectional PIO Controller C line 11; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
93 PA16/PGMD8 bidirectional PIO Controller A line 16, with alternate parallel-programming function PGMD8 (see Section 21, FFPI); also SPI NPCS0 per Table 31-2.
94 PC12 bidirectional PIO Controller C line 12; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
95 PA17/PGMD9 bidirectional PIO Controller A line 17, with alternate parallel-programming function PGMD9 (see Section 21, FFPI).
96 PB16 bidirectional PIO Controller B line 16; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
97 PB15 bidirectional PIO Controller B line 15; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
98 PC13 bidirectional PIO Controller C line 13; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
99 PA18/PGMD10 bidirectional PIO Controller A line 18, with alternate parallel-programming function PGMD10 (see Section 21, FFPI).
100 PA19/PGMD11 bidirectional PIO Controller A line 19, with alternate parallel-programming function PGMD11 (see Section 21, FFPI).
101 PA20/PGMD12 bidirectional PIO Controller A line 20, with alternate parallel-programming function PGMD12 (see Section 21, FFPI).
102 PA21/PGMD13 bidirectional PIO Controller A line 21, with alternate parallel-programming function PGMD13 (see Section 21, FFPI).
103 PA23/PGMD15 bidirectional PIO Controller A line 23, with alternate parallel-programming function PGMD15 (see Section 21, FFPI).
104 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
105 PA24 bidirectional PIO Controller A line 24; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
106 PA25 bidirectional PIO Controller A line 25; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
107 PA26 bidirectional PIO Controller A line 26; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
108 PC20 bidirectional PIO Controller C line 20; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
109 PA0/PGMNCMD bidirectional PIO Controller A line 0, with alternate parallel-programming function PGMNCMD (see Section 21, FFPI).
110 PC0 bidirectional PIO Controller C line 0; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
111 PA1/PGMRDY bidirectional PIO Controller A line 1, with alternate parallel-programming function PGMRDY (see Section 21, FFPI).
112 PC1 bidirectional PIO Controller C line 1; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
113 PA2/PGMNOE bidirectional PIO Controller A line 2, with alternate parallel-programming function PGMNOE (see Section 21, FFPI).
114 PC2 bidirectional PIO Controller C line 2; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
115 PA3/PGMNVALID bidirectional PIO Controller A line 3, with alternate parallel-programming function PGMNVALID (see Section 21, FFPI).
116 PC3 bidirectional PIO Controller C line 3; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
117 PA4/PGMM0 bidirectional PIO Controller A line 4, with alternate parallel-programming function PGMM0 (see Section 21, FFPI).
118 PC4 bidirectional PIO Controller C line 4; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
119 PA5/PGMM1 bidirectional PIO Controller A line 5, with alternate parallel-programming function PGMM1 (see Section 21, FFPI).
120 PC5 bidirectional PIO Controller C line 5; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
121 PA6/PGMM2 bidirectional PIO Controller A line 6, with alternate parallel-programming function PGMM2 (see Section 21, FFPI).
122 PC6 bidirectional PIO Controller C line 6; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
123 PA7/PGMM3 bidirectional PIO Controller A line 7, with alternate parallel-programming function PGMM3 (see Section 21, FFPI).
124 PC7 bidirectional PIO Controller C line 7; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
125 VDDCORE power_in Powers the core, embedded memories and peripherals; voltage range 1.62-1.95 V.
126 GND power_in Ground common to the VDDCORE and VDDIO supplies.
127 VDDIO power_in Powers the peripheral I/O lines; voltage range 1.62-3.6 V.
128 PA8/PGMD0 bidirectional PIO Controller A line 8, with alternate parallel-programming function PGMD0 (see Section 21, FFPI); also HSMCI MCDA3 per Table 36-2.
129 PC8 bidirectional PIO Controller C line 8; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
130 PA9/PGMD1 bidirectional PIO Controller A line 9, with alternate parallel-programming function PGMD1 (see Section 21, FFPI); also TWI0 TWD0 per Table 32-4.
131 PC9 bidirectional PIO Controller C line 9; peripheral alternate functions are defined in Section 11.2, which is not in the provided text.
132 PA10/PGMD2 bidirectional PIO Controller A line 10, with alternate parallel-programming function PGMD2 (see Section 21, FFPI); also TWI0 TWCK0 per Table 32-4.
133 PA11/PGMD3 bidirectional PIO Controller A line 11, with alternate parallel-programming function PGMD3 (see Section 21, FFPI); also UART URXD per Table 33-2.
134 PA12/PGMD4 bidirectional PIO Controller A line 12, with alternate parallel-programming function PGMD4 (see Section 21, FFPI); also UART UTXD per Table 33-2.
135 FWUP input Fast wake-up input feeding a falling-edge detector; it is one of the pins that must be high (with NRST, NRSTB and JTAGSEL) to enable JTAG boundary scan.
136 SHDN output Shutdown control pin, listed with FWUP in the backup supply schemes, used to manage an external switch for the supplies in Backup mode.
137 ERASE input ERASE pin used for Flash content erase/reprogramming; the detailed behaviour in Section 6.7 is not in the provided text.
138 TST input Test select: low at power-up selects normal operation, high selects test or FFPI mode; it has an internal ~15 kΩ pull-down and may be left unconnected in normal use.
139 VDDBU power_in Powers the Slow Clock oscillator and part of the System Controller; voltage range 1.62-3.6 V, and must be supplied before or at the same time as VDDIO and VDDCORE.
140 GNDBU power_in Separate ground for VDDBU, which powers the Slow Clock oscillator and part of the System Controller.
141 NRSTB input Reset input that must be high, together with FWUP, NRST and JTAGSEL, to enable JTAG boundary scan while TST is low.
142 JTAGSEL input JTAG/SWD debug port selection: SW-DP or JTAG-DP is selected when low, and a chip reset is required after changing it.
143 XOUT32 output Output of the 32.768 kHz crystal oscillator; leave unconnected if the crystal oscillator is not used.
144 XIN32 input Input of the 32.768 kHz crystal oscillator; it can also take an external clock in bypass mode (OSCBYPASS set).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-144(20x20)
Category Single Chip Microcomputer/Microcontroller
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDDCORE supply voltage range VDDCORE 1.62 1.95 V Powers core, embedded memories and peripherals 17
VDDIO supply voltage range VDDIO 1.62 3.6 V Powers peripheral I/O lines 17
VDDBU supply voltage range VDDBU 1.62 3.6 V Powers Slow Clock oscillator and part of System Controller 17
VDDPLL supply voltage range VDDPLL 1.62 1.95 V Powers PLL A, UPLL and 3-20 MHz Oscillator 17
VDDUTMI supply voltage range VDDUTMI 3 3.3 3.6 V Powers UTMI+ interface; 3.3V nominal 17
VDDANA supply voltage range VDDANA 2 3.6 V Powers ADC cells 17
VDDIO minimum operating voltage 1.6 V VDDIO must reach this before VDDCORE reaches VDDCORE(min) 17
Voltage regulator static current, Normal mode 700 uA Normal mode, static current (stated as less than) 18
Voltage regulator output current 150 mA Normal mode, output current 18
Voltage regulator consumption, Shutdown mode 1 uA Shutdown mode (stated as less than) 18
Voltage regulator startup time to Normal mode 400 us Startup to reach Normal mode (stated as inferior to) 18
Voltage regulator default output voltage 1.8 V Default output voltage 18
Backup mode current consumption 2.5 uA Backup mode; current consumption on VDDBU 24
Backup mode wake-up time 0.5 ms Backup mode wake-up until first instruction fetched (stated as less than) 24
Wait mode wake-up time 10 us Wait mode wake-up until first instruction fetched (stated as less than) 24
High-speed I/O maximum frequency, HSMCI and SPI clock lines 65 MHz HSMCI and SPI clock lines 25
I/O maximum frequency, other lines 35 MHz Other I/O lines 25
Internal I/O pull-up resistor 100 kOhm Typical pull-up value for all I/Os 25
On-die termination series resistor RODT 36 Ohm ODT, typical, per Figure 6-1 25
NRST internal pull-up resistor 100 kOhm Permanent pull-up to VDDIO, about 100 kOhm 26
NRSTB internal pull-up resistor 15 kOhm Permanent pull-up, about 15 kOhm 26
JTAGSEL internal pull-down resistor 15 kOhm Permanent pull-down to GNDBU, about 15 kOhm 26
TST internal pull-down resistor 15 kOhm Permanent pull-down to GND, about 15 kOhm 26
ERASE internal pull-down resistor 15 kOhm Permanent pull-down to GND, about 15 kOhm 26
ERASE pin reinitialization hold time 220 ms ERASE tied high for more than 220 ms to reinitialize Flash 27
ERASE pin glitch rejection 100 ms ERASE tied high for less than 100 ms is not taken into account 27
External reset assertion length, minimum 60 us Programmable via ERSTL, assertion duration between 60 us and 2 seconds 237
External reset assertion length, maximum 2 seconds Programmable via ERSTL, assertion duration between 60 us and 2 seconds 237
Slow clock RC oscillator frequency SLCK 22 42 kHz Low Power RC Oscillator 264
Supply monitor threshold on VDDUTMI SMTH 1.9 3.4 V Programmable in 100 mV steps via SUPC_SMMR 269
3-20 MHz crystal oscillator maximum startup time 62 ms MOSCXTCNT 8-bit value; stated as about 62 ms 446
Operating temperature range, Industrial -40 85 °C Industrial grade, ordering code ATSAM3U4EA-AU, LQFP144 1137

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the 134

CAD (KiCad official)

  • Symbol: ATSAM3U4EA-AU
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: atsam3u4ea-au-etched.step / atsam3u4ea-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam3u4ea-au.step / atsam3u4ea-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1163 pp, sha256 b84d00c06a823c14, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF