component
2N7002KDTL
Public Made by Adomby adom
Siliup MOSFETs, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown2N7002KDTL
Siliup · MOSFETs · SOT-563
2N7002KDTL from Siliup, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel, 60V VDSS, 300mA continuous drain current). |
| 2 | G1 | input | Gate of MOSFET 1, ESD protected 2KV, with gate-source voltage limit of ±20V. |
| 3 | D2 | passive | Drain of MOSFET 2 (N-channel, 60V VDSS, 300mA continuous drain current). |
| 4 | S2 | passive | Source of MOSFET 2 (N-channel, 60V VDSS, 300mA continuous drain current). |
| 5 | G2 | input | Gate of MOSFET 2, ESD protected 2KV, with gate-source voltage limit of ±20V. |
| 6 | D1 | passive | Drain of MOSFET 1 (N-channel, 60V VDSS, 300mA continuous drain current). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Siliup |
| Package | SOT-563 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | 60 | V | 2 | |||
| Gate-Source Voltage | VGSS | -20 | 20 | V | 2 | ||
| Continuous Drain Current | ID | 300 | mA | 2 | |||
| Pulse Drain Current Tested | IDM | 1200 | mA | 2 | |||
| Power Dissipation | PD | 150 | mW | 2 | |||
| Storage Temperature Range | TSTG | -55 | 150 | °C | 2 | ||
| Operating Junction Temperature Range | TJ | -55 | 150 | °C | 2 | ||
| Thermal Resistance Junction-to-Ambient | RθJA | 833 | °C/W | 2 | |||
| Drain-Source Breakdown Voltage | BVDSS | 60 | V | VGS=0V, ID=250µA | 2 | ||
| Drain-Source Leakage Current | IDSS | 1 | uA | VDS=48V, VGS=0V | 2 | ||
| Gate-Source Leakage Current | IGSS | -10 | 10 | uA | VGS=±20V, VDS=0V | 2 | |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2.5 | V | VDS=VGS, ID=250µA | 2 |
| Static Drain-Source On-Resistance at VGS=10V | RDS(ON) | 1.7 | 3 | Ω | VGS =10V, ID =200mA | 2 | |
| Static Drain-Source On-Resistance at VGS=4.5V | RDS(ON) | 1.8 | 4 | Ω | VGS =4.5V, ID =200mA | 2 | |
| Diode Forward Voltage | VSD | 1.2 | V | VGS=0V, IS=1A, TJ=25℃ | 2 |
CAD (KiCad official)
- Symbol:
2N7002KDTL - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
2n7002kdtl-etched.step/2n7002kdtl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);2n7002kdtl.step/2n7002kdtl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Siliup datasheet (5 pp, sha256
dedac415f2064eed, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).