STM32L431KCU6 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Standard operating voltage of 1.71 V to 3.6 V (Table 22).
2	PC14-OSC32_IN	bidirectional	FT I/O supplied through the power switch, which sinks only 3 mA, so output use is limited to 2 MHz at 30 pF and it must not source current; also serves as the OSC32_IN input.
3	PC15-OSC32_OUT	bidirectional	FT I/O supplied through the power switch, which sinks only 3 mA, so output use is limited to 2 MHz at 30 pF and it must not source current; also serves as the OSC32_OUT output.
4	NRST	bidirectional	Bidirectional reset pin with an embedded weak pull-up resistor.
5	VDDA/VREF+	power_in	Analog supply of 1.62 V to 3.6 V when the ADC or COMP is used (Table 22); also functions as the VREF+ reference input.
6	PA0/CK_IN	bidirectional	5 V tolerant analog-switch I/O (FT_a) with TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK and TIM2_ETR alternate functions, plus ADC1_IN5 and CK_IN.
7	PA1	bidirectional	5 V tolerant analog-switch I/O (FT_a) with TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE and TIM15_CH1N alternate functions, plus ADC1_IN6.
8	PA2	bidirectional	5 V tolerant analog-switch I/O (FT_a) with TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS and TIM15_CH1 alternate functions, plus ADC1_IN7 and WKUP4.
9	PA3	bidirectional	3.6 V tolerant analog-switch I/O (TT_a) with TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK and SAI1_MCLK_A alternate functions, plus ADC1_IN8.
10	PA4	bidirectional	3.6 V tolerant analog-switch I/O (TT_a) with SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B and LPTIM2_OUT alternate functions, plus ADC1_IN9 and DAC1_OUT1.
11	PA5	bidirectional	3.6 V tolerant analog-switch I/O (TT_a) with TIM2_CH1, TIM2_ETR, SPI1_SCK and LPTIM2_ETR alternate functions, plus ADC1_IN10 and DAC1_OUT2.
12	PA6	bidirectional	5 V tolerant analog-switch I/O (FT_a) with TIM1_BKIN, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3 and TIM16_CH1 alternate functions, plus ADC1_IN11.
13	PA7	bidirectional	5 V tolerant I/O with Fm+ capability (FT_fa) with TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2 and COMP2_OUT alternate functions, plus ADC1_IN12.
14	PB0	bidirectional	5 V tolerant analog-switch I/O (FT_a) with TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT and SAI1_EXTCLK alternate functions, plus ADC1_IN15.
15	PB1	bidirectional	5 V tolerant analog-switch I/O (FT_a) with TIM1_CH3N, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0 and LPTIM2_IN1 alternate functions, plus COMP1_INM and ADC1_IN16.
16	VSS	power_in	Ground pin.
17	VDD	power_in	Standard operating voltage of 1.71 V to 3.6 V (Table 22).
18	PA8	bidirectional	5 V tolerant I/O (FT) with MCO, TIM1_CH1, USART1_CK, SWPMI1_IO, SAI1_SCK_A and LPTIM2_OUT alternate functions.
19	PA9	bidirectional	5 V tolerant I/O with Fm+ capability (FT_f) with TIM1_CH2, I2C1_SCL, USART1_TX, SAI1_FS_A and TIM15_BKIN alternate functions.
20	PA10	bidirectional	5 V tolerant I/O with Fm+ capability (FT_f) with TIM1_CH3, I2C1_SDA, USART1_RX and SAI1_SD_A alternate functions.
21	PA11	bidirectional	5 V tolerant I/O (FT) with TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS and CAN1_RX alternate functions.
22	PA12	bidirectional	5 V tolerant I/O (FT) with TIM1_ETR, SPI1_MOSI, USART1_RTS_DE and CAN1_TX alternate functions.
23	PA13 (JTMS-SWDIO)	bidirectional	5 V tolerant I/O (FT) that after reset is configured as the JTMS-SWDIO debug function with an internal pull-up enabled.
24	PA14 (JTCK-SWCLK)	bidirectional	5 V tolerant I/O (FT) that after reset is configured as the JTCK-SWCLK debug function with an internal pull-down enabled.
25	PA15 (JTDI)	bidirectional	5 V tolerant I/O (FT) that after reset is configured as the JTDI debug function with an internal pull-up enabled.
26	PB3 (JTDO-TRACESWO)	bidirectional	5 V tolerant analog-switch I/O (FT_a) that after reset is configured as the JTDO-TRACESWO debug function, with TIM2_CH2, SPI1_SCK and SAI1_SCK_B alternate functions and COMP2_INM.
27	PB4 (NJTRST)	bidirectional	5 V tolerant I/O with Fm+ and analog-switch capability (FT_fa) that after reset is configured as NJTRST with an internal pull-up enabled, with I2C3_SDA, SPI1_MISO and TSC_G2_IO1 alternate functions and COMP2_INP.
28	PB5	bidirectional	5 V tolerant I/O (FT) with LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B and TIM16_BKIN alternate functions.
29	PB6	bidirectional	5 V tolerant I/O with Fm+ and analog-switch capability (FT_fa) with LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, SAI1_FS_B and TIM16_CH1N alternate functions, plus COMP2_INP.
30	PB7	bidirectional	5 V tolerant I/O with Fm+ and analog-switch capability (FT_fa) with LPTIM1_IN2, I2C1_SDA, USART1_RX and TSC_G2_IO4 alternate functions, plus COMP2_INM and PVD_IN.
31	PH3/BOOT0	bidirectional	5 V tolerant I/O (FT) that also provides the BOOT0 boot-mode pin.
32	VSS	power_in	Ground pin.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	UFQFPN-32(5x5)
Category	Embedded Processors & Controllers
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Standard operating voltage	VDD	1.71		3.6	V	-	88
Analog supply voltage, ADC or COMP used	VDDA	1.62		3.6	V	ADC or COMP used	88
Analog supply voltage, DAC or OPAMP used	VDDA	1.8		3.6	V	DAC or OPAMP used	88
Analog supply voltage, VREFBUF used	VDDA	2.4		3.6	V	VREFBUF used	88
Backup operating voltage	VBAT	1.55		3.6	V	-	88
Internal AHB clock frequency	fHCLK	0		80	MHz	-	88
Internal APB1 clock frequency	fPCLK1	0		80	MHz	-	88
Internal APB2 clock frequency	fPCLK2	0		80	MHz	-	88
Ambient temperature for the suffix 6 version	TA	-40		85	°C	Maximum power dissipation	88
Ambient temperature for the suffix 6 version, low-power dissipation	TA	-40		105	°C	Low-power dissipation	88
Junction temperature range, suffix 6 version	TJ	-40		105	°C	Suffix 6 version	88
Power dissipation UFQFPN32	PD			523	mW	TA = 85 °C for suffix 6	88
I/O input voltage, all I/O except TT_xx	VIN	-0.3			V	Max = Min(Min(VDD, VDDA)+3.6 V, 5.5 V)	88
I/O input voltage, TT_xx I/O	VIN	-0.3			V	Max = VDDIOx+0.3	88
External main supply voltage (including VDD, VDDA, VBAT)	VDDX - VSS	-0.3		4	V	-	86
Input voltage on any other pins	VIN	-0.3		4	V	-	86
Variations between different VDDX power pins of the same domain	/ΔVDDx/			50	mV	-	86
Total current into sum of all VDD power lines (source)	∑IVDD			140	mA	-	87
Total current out of sum of all VSS ground lines (sink)	∑IVSS			140	mA	-	87
Maximum current into each VDD power pin (source)	IVDD(PIN)			100	mA	-	87
Maximum current out of each VSS ground pin (sink)	IVSS(PIN)			100	mA	-	87
Output current sunk by any I/O and control pin except FT_f	IIO(PIN)			20	mA	-	87
Output current sunk by any FT_f pin	IIO(PIN)			20	mA	-	87
Output current sourced by any I/O and control pin	IIO(PIN)			20	mA	-	87
Total output current sunk by sum of all I/Os and control pins	∑IIO(PIN)			100	mA	-	87
Total output current sourced by sum of all I/Os and control pins	∑IIO(PIN)			100	mA	-	87
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5	IINJ(PIN)	-5		0	mA	-	87
Injected current on PA4, PA5	IINJ(PIN)	-5		0	mA	-	87
Total injected current (sum of all I/Os and control pins)	∑/IINJ(PIN)/			25	mA	-	87
Storage temperature range	TSTG	-65		150	°C	-	87
Maximum junction temperature	TJ			150	°C	-	87
Internal 16 MHz factory-trimmed RC accuracy	-	-1		1	%	Internal 16 MHz factory-trimmed RC	1
Internal low-power 32 kHz RC accuracy	-	-5		5	%	Internal low-power 32 kHz RC	1
Internal reference voltage	VREFINT	1.182	1.212	1.232	V	-40 °C < TA < +130 °C	91
Reference voltage spread over the temperature range	ΔVREFINT		5	7.5	mV	VDD = 3 V	91
Temperature coefficient	TCoeff		30	50	ppm/°C	-40°C < TA < +130°C	91
Long term stability	ACoeff		300	1000	ppm	1000 hours, T = 25°C	91
Voltage coefficient	VDDCoeff		250	1200	ppm/V	3.0 V < VDD < 3.6 V	91
1/4 reference voltage	VREFINT_DIV1	24	25	26	% VREFINT	-	91
1/2 reference voltage	VREFINT_DIV2	49	50	51	% VREFINT	-	91
3/4 reference voltage	VREFINT_DIV3	74	75	76	% VREFINT	-	91
ADC sampling time when reading the internal reference voltage	tS_vrefint	4			µs	-	91
Start time of reference voltage buffer when ADC is enabled	tstart_vrefint		8	12	µs	-	91
VREFINT buffer consumption from VDD when converted by ADC	IDD(VREFINTBUF)		12.5	20	µA	-	91
Reset temporization after BOR0 is detected	tRSTTEMPO	250		400	µs	VDD rising	89
Brown-out reset threshold 0 rising edge	VBOR0	1.62	1.66	1.7	V	Rising edge	89
Brown-out reset threshold 0 falling edge	VBOR0	1.6	1.64	1.69	V	Falling edge	89
Brown-out reset threshold 1 rising edge	VBOR1	2.06	2.1	2.14	V	Rising edge	89
Brown-out reset threshold 1 falling edge	VBOR1	1.96	2	2.04	V	Falling edge	89
Supply current in Run mode, 80 MHz, 25 °C	IDD_ALL(Run)		8.53	9.5	mA	Range 1, fHCLK = 80 MHz, all peripherals disabled, 25 °C	94
Supply current in Run mode, 80 MHz, 125 °C	IDD_ALL(Run)		8.92	10.3	mA	Range 1, fHCLK = 80 MHz, all peripherals disabled, 125 °C	94
Supply current in Sleep mode, 80 MHz, 25 °C	IDD_ALL(Sleep)		2.23	2.5	mA	Range 1, fHCLK = 80 MHz, all peripherals disabled, 25 °C	99
Supply current in low-power run mode, 2 MHz, 25 °C	IDD_ALL(LPRun)		211	273.8	µA	fHCLK = fMSI = 2 MHz, all peripherals disabled, 25 °C	94
Supply current in Stop 2 mode, RTC disabled, 25 °C	IDD_ALL(Stop 2)		1.06	2.1	µA	VDD = 3 V, 25 °C, RTC disabled	100
Supply current in Standby mode, RTC disabled, 25 °C	IDD_ALL(Standby)		90.2	225	nA	VDD = 3 V, 25 °C, no independent watchdog	104
Supply current in Standby mode, RTC disabled, 25 °C	IDD_ALL(Standby)		27.7	119	nA	VDD = 1.8 V, 25 °C, no independent watchdog	104
Supply current in Shutdown mode, RTC disabled, 25 °C	IDD_ALL(Shutdown)		44.3	70.1	nA	VDD = 3 V, 25 °C, RTC disabled	105
Backup domain supply current, RTC disabled, 25 °C	IDD_VBAT(VBAT)		5	12.5	nA	VBAT = 3 V, 25 °C, RTC disabled	107
Wakeup time from Sleep mode to Run mode	tWUSLEEP		66		Nb of CPU cycles	-	111

CAD (KiCad official)

Symbol: STM32L431KCU6
Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
3D model: UFQFPN-32(5x5) (KiCad packages3D, STEP)
3D model files: stm32l431kcu6-etched.step / stm32l431kcu6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l431kcu6.step / stm32l431kcu6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (208 pp, sha256 71963de3cb899f8f, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STM32L431KCU6

Verified STM32L431KCU6

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README