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SN74F10N

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Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74F10N

Texas Instruments · Logic Gates · PDIP-14

SN74F10N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of NAND gate 1 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
2 1B input Input B of NAND gate 1 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
3 2A input Input A of NAND gate 2 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
4 2B input Input B of NAND gate 2 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
5 2C input Input C of NAND gate 2 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
6 2Y output Output of NAND gate 2; rated for a low-level output current IOL of up to 20 mA and high-level output current IOH of -1 mA.
7 GND power_in Ground reference pin for the device.
8 3Y output Output of NAND gate 3; rated for a low-level output current IOL of up to 20 mA and high-level output current IOH of -1 mA.
9 3A input Input A of NAND gate 3 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
10 3B input Input B of NAND gate 3 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
11 3C input Input C of NAND gate 3 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
12 1Y output Output of NAND gate 1; rated for a low-level output current IOL of up to 20 mA and high-level output current IOH of -1 mA.
13 1C input Input C of NAND gate 1 (Y = A·B·C); logic-high needs VIH of at least 2 V and logic-low is VIL of at most 0.8 V.
14 VCC power_in Supply voltage, 4.5 V minimum to 5.5 V maximum with 5 V nominal, per recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 2
Input voltage range VI -1.2 7 V see Note 1 2
Input current range -30 5 mA 2
Voltage applied to any output in the high state -0.5 V output high state; upper limit printed as VCC 2
Current into any output in the low state 40 mA 2
Operating free-air temperature range, SN74F10 TA 0 70 °C 2
Storage temperature range -65 150 °C 2
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input clamp current IIK -18 mA 2
High-level output current IOH -1 mA 2
Low-level output current IOL 20 mA 2
Operating free-air temperature TA 0 70 °C SN74F10 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 2
High-level output voltage VOH 2.5 3.4 V VCC = 4.5 V, IOH = -1 mA 2
High-level output voltage VOH 2.7 V VCC = 4.75 V, IOH = -1 mA 2
Low-level output voltage VOL 0.3 0.5 V VCC = 4.5 V, IOL = 20 mA 2
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 2
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 2
Low-level input current IIL -0.6 mA VCC = 5.5 V, VI = 0.5 V 2
Short-circuit output current IOS -60 -150 mA VCC = 5.5 V, VO = 0 2
Supply current, outputs high ICCH 1.4 2.1 mA VCC = 5.5 V, VI = 0 2
Supply current, outputs low ICCL 5.1 7.7 mA VCC = 5.5 V, VI = 4.5 V 2
Propagation delay low-to-high tPLH 1.6 6 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay high-to-low tPHL 1 5.3 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay low-to-high tPLH 1.6 3.3 5 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C 3
Propagation delay high-to-low tPHL 1 2.8 4.3 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C 3

CAD (KiCad official)

  • Symbol: SN74F10N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74f10n-etched.step / sn74f10n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f10n.step / sn74f10n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 906d204aa757f1d6, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF