MC33FS6523NAE from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSUP1	power_in	Device power supply behind a mandatory external reverse battery protection diode, to be tied to VSUP2; absolute maximum -1.0 to 40 V.
2	VSUP2	power_in	Second supply input protected by the same reverse battery diode as VSUP1 and connected to VSUP1 externally.
3	VSENSE	input	Battery voltage sensing input connected before the reverse battery diode through a mandatory series resistor; -14 to 40 V.
4	VSUP3	power_in	Third device supply input, connected between the reverse protection diode and the input PI filter.
5	FS1B	output	Second active-low open-drain safety output, asserted low at start-up and on fault with configurable delay or duration versus FS0B.
6	GND_COM	power_in	Dedicated ground for the physical layers.
7	CAN_5V	power_out	Output voltage of the embedded CAN FD interface regulator.
8	n.c.	unconnected	Not connected (no CAN physical interface on this variant; CANH position).
9	n.c.	unconnected	Not connected (no CAN physical interface on this variant; CANL position).
10	IO_4	bidirectional	Load-dump-proof digital input with wake-up capability or low-side logic-level NMOS gate driver output controlled by SPI; use a series resistor, -0.3 to 40 V.
11	IO_5/VKAM	bidirectional	Digital/analog input with wake-up capability or keep-alive memory supply output in low-power mode; -0.3 to 20 V.
12	IO_0	bidirectional	Analog or digital input (load dump proof) with selectable wake-up capability; series resistor mandatory, -0.3 to 40 V.
13	FCRBM	input	Feedback core resistor bridge monitoring input for the redundant VCORE divider midpoint; connect directly to FB_CORE if unused.
14	FS0B	output	First active-low open-drain safety output asserted low at start-up and on fault; external pull-up mandatory.
15	DEBUG	input	Debug mode entry input, sampled at start-up; -0.3 to 40 V.
16	AGND	power_in	Analog ground connection.
17	MUX_OUT	output	Multiplexed analog output to an MCU ADC, selected through SPI.
18	IO_2	input	Logic-level digital input with selectable wake-up capability, readable by SPI and usable for FCCU error monitoring.
19	IO_3	input	Logic-level digital input with selectable wake-up capability, readable by SPI and usable for FCCU error monitoring.
20	n.c.	unconnected	Not connected (no CAN physical interface on this variant; TXD position).
21	n.c.	unconnected	Not connected (no CAN physical interface on this variant; RXD position).
22	VPU_FS	power_out	Pull-up output for the FS1B function, internally attached to VPRE through a reverse diode.
23	n.c.	unconnected	Not connected (no LIN interface on this variant; RXDL position).
24	RSTB	bidirectional	Active-low open-drain reset output to the MCU, asserted on safety block failure; input is monitored for external reset; pull-up to VDDIO required.
25	MISO	output	SPI data output, buffer supplied from VDDIO.
26	MOSI	input	SPI data input.
27	SCLK	input	SPI serial clock input.
28	NCS	input	SPI chip select input, active low.
29	INTB	output	Interrupt output generating a configurable-duration low pulse, with internal pull-up to VDDIO.
30	VDDIO	power_in	Supply input for the MISO output buffer for MCU I/O voltage compatibility; -0.3 to 8 V.
31	SELECT	input	Hardware selection input setting VAUX and VCCA output voltages (3.3 V or 5.0 V) via an external resistor to GND or VPRE.
32	FB_CORE	input	VCORE voltage feedback input to the error amplifier; -0.3 to 2.5 V.
33	COMP_CORE	output	Error amplifier output for the VCORE compensation network (FS6500 series).
34	VCORE_SNS	input	VCORE input voltage sense; 0 to 8 V.
35	SW_CORE	output	VCORE SMPS switching output point (FS6500 series).
36	BOOT_CORE	passive	Bootstrap capacitor connection for the VCORE internal NMOS gate drive; 0 to 15 V.
37	VPRE	power_in	VPRE pre-regulator output/input voltage sense, -0.3 to 8 V.
38	VAUX	output	VAUX output voltage, external PNP ballast collector connection.
39	VAUX_B	output	VAUX regulator external PNP ballast base connection.
40	VAUX_E	output	VAUX regulator external PNP ballast emitter connection.
41	VCCA_E	output	VCCA regulator external PNP ballast emitter connection.
42	VCCA_B	output	VCCA regulator external PNP ballast base connection.
43	VCCA	power_out	VCCA output voltage (5.0 V or 3.3 V), external PNP ballast collector connection.
44	GATE_LS	output	Low-side MOSFET gate drive for the non-inverting buck-boost configuration; tie to PGND for buck.
45	DGND	power_in	Digital ground connection.
46	BOOT_PRE	passive	Bootstrap capacitor connection for the VPRE internal NMOS gate drive; -1.0 to 50 V.
47	SW_PRE2	output	Second pre-regulator switching output point.
48	SW_PRE1	output	First pre-regulator switching output point.

Key specifications

Parameter	Value
Manufacturer	NXP Semicon
Package	LQFP-48(7x7)
Category	Power Management ICs
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ambient temperature	TA	-40		125	°C		16
Junction temperature	TJ	-40		150	°C		16
Storage temperature	TSTG	-55		150	°C		16
ESD human body model, LIN pins	VESD-HBM4	-8		8	kV	LIN pins	16
ESD charge device model, all pins	VESD-CDM1	-500		500	V	Charge device model (JESD22/C101), all pins	16
Power supply current in normal mode	ISUP123			15	mA		17
Power supply current for VSUP3 in normal mode	ISUP3		3.5	5	mA		17
Power supply current in LPOFF	ISUP_LPOFF2		42	60	µA	VSUP = 18 V at TA = 80 °C	17
Power supply undervoltage warning	VSNS_UV	7	8	9	V		17
Power supply undervoltage lockout (power up)	VSUP_UV_7	7		8	V		17
Power supply undervoltage lockout (falling) - boost configuration	VSUP_UV_L			2.7	V		17
Power supply undervoltage lockout (falling) - buck configuration	VSUP_UV_L_B			4.5	V		17
VPRE output voltage (buck mode)	VPRE	6.25		6.75	V	Buck mode (VSUP > VSUP_UV_7)	17
VPRE output voltage (boost mode)	VPRE	6		7	V	Boost mode (VSUP ≥ 2.7 V)	17
SW_PRE output current limitation in buck-boost mode	IPRE_LIM1	3.5			A	VSUP ≤ 28 V	17
SW_PRE output current limitation in buck mode	IPRE_LIM2	2.5			A	VSUP ≤ 28 V	17
SW_PRE overcurrent detection threshold in buck mode	IPRE_OC	4.5			A	VSUP ≤ 28 V	17
VPRE undervoltage detection threshold (falling)	VPRE_UV	5.5		6	V		17
VPRE pass transistor on resistance	RDSON_PRE			200	mΩ	VSUP ≤ 28 V	18
VPRE thermal shutdown threshold	TSD_PRE	160			°C		18
LS gate driver low level	VG_LS_OL			0.5	V	IOUT = 50 mA	18
VCORE feedback input voltage	VCORE_FB	0.784	0.8	0.816	V		18
VCORE internal pull-down current	IPD_CORE	5	12	25	mA	active when VCORE is enabled	18
VCORE output current capability in normal mode	ICORE			2.2	A	FS652x	18
VCORE output current limitation	ICORE_LIM	2.5		3.5	A	FS652x	18
VCORE pass transistor on resistance	RDSON_CORE			200	mΩ		18
VCORE transient load regulation - 1.2 V range	FS65_LORVCORE_1.2	-60		60	mV	COUT_VCORE = 40 µF, ICORE = 10 mA to 2.2 A, dICORE/dt ≤ 2.0 A/µs	18
VCORE thermal shutdown threshold	TSD_CORE	160			°C		19
VCCA output voltage (5.0 V, internal ballast)	VCCA	4.95	5	5.05	V	5.0 V configuration with Internal ballast at 100 mA	19
VCCA output voltage (5.0 V, external ballast)	VCCA	4.9	5	5.1	V	5.0 V configuration with external ballast at 200 mA	19
VCCA output voltage (3.3 V, internal ballast)	VCCA	3.267	3.3	3.333	V	3.3 V configuration with Internal ballast at 100 mA	19
VCCA output current (int. MOSFET)	ICCA_IN			100	mA		19
VCCA output current limitation (int. MOSFET)	ICCA_LIM_INT	100		675	mA		19
VCCA output current limitation (external PNP)	ICCA_LIM_OUT	300		675	mA		19
VCCA thermal shutdown threshold (int. MOSFET only)	TSDCCA	160			°C		19
VAUX output voltage (5.0 V configuration)	VAUX_5	4.85	5	5.15	V	5.0 V configuration	19
VAUX output voltage (3.3 V configuration)	VAUX_33	3.2	3.3	3.4	V	3.3 V configuration	19
VAUX output current	IAUX_OUT			400	mA		19
VAUX output current limitation	IAUX_LIM	400		800	mA		20
VAUX tracking error (VAUX_5 and VAUX_33)	VAUX_TRK	-15		15	mV		19
VCAN output voltage	VCAN	4.8	5	5.2	V	VSUP > 6.0 V in buck mode; VSUP > VSUP_UV_L in boost mode	20
VCAN output current	ICAN_OUT			100	mA		20
VKAM output voltage	VKAM	3	3.5	4	V		20
VKAM output current	IKAM_OUT			3	mA		20
VPRE overvoltage detection threshold	VPRE_OV	7.2		8	V		20
VCORE FB undervoltage detection threshold	VCORE_FB_UV	0.67		0.773	V		20
VCORE FB overvoltage detection threshold	VCORE_FB_OV	0.84		0.905	V		21
VCCA undervoltage detection threshold (5.0 V configuration)	VCCA_UV_5	4.5		4.75	V	5.0 V configuration	21
VCCA overvoltage detection threshold (5.0 V configuration)	VCCA_OV_5	5.25		5.5	V	5.0 V configuration	21
VAUX undervoltage detection threshold (5.0 V configuration)	VAUX_UV_5	4.5		4.75	V	5.0 V configuration	21
Reset low output level	VRSTB_OL			0.5	V	I_RSTB = 2.0 mA	21
Reset high level detection threshold (rising)	VRSTB_IH			2	V		21
FS0B low output level	VFS0B_OL			0.5	V	I_FS0B = 2.0 mA	21
Digital high input voltage level (IO_0, IO_4, IO_5)	VIO_IH	2.6			V	IO_0, IO_4, IO_5	22
Digital low input voltage level (IO_0, IO_4, IO_5)	VIO_IL			2.1	V	IO_0, IO_4, IO_5	22
SCLK, NCS, MOSI high input threshold	VSPI_IH	2			V	SCLK, NCS, MOSI	23
SCLK, NCS, MOSI low input threshold	VSPI_IL			0.8	V	SCLK, NCS, MOSI	23
Thermal resistance junction to ambient	RθJA		30		°C/W	JEDEC JESD51-6, board JESD51-7 horizontal	16
Thermal resistance junction to case top	RθJCTOP		23.8		°C/W	cold plate method (MIL SPEC-883 Method 1012.1)	16
Thermal resistance junction to case bottom	RθJCBOTTOM		0.9		°C/W	simulation without any interface resistance	16

CAD (KiCad official)

Symbol: MC33FS6523NAE
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: mc33fs6523nae-etched.step / mc33fs6523nae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc33fs6523nae.step / mc33fs6523nae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NXP Semicon datasheet (161 pp, sha256 39f5c318b818b984, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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MC33FS6523NAE

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