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ATMEGA4808-MUR

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleratmega4808-murfactory-2.0.0extractor-text

Verified ATMEGA4808-MUR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA4808-MUR · VQFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 560-page datasheet
  • ✓distributor: lcsc C2055547, digikey 150-ATMEGA4808-MURTR-ND, mouser 556-ATMEGA4808-MUR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-t2710f3z/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega4808-mur.kicad_sym✓ atmega4808-mur.kicad_mod✓ atmega4808-mur.step
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Symbol & Footprint

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Contents

README

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ATMEGA4808-MUR

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)

ATMEGA4808-MUR from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions TWI0 SCL/SDA, USART0 XDIR, TCA0 WO3, and CCL LUT0 OUT.
2 PA4 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions USART0 TxD, SPI0 MOSI, and TCA0 WO4.
3 PA5 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions USART0 RxD, SPI0 MISO, and TCA0 WO5.
4 PA6 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions USART0 XCK, SPI0 SCK, and CCL LUT0 OUT.
5 PA7 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions CLKOUT, AC0 OUT, USART0 XDIR, SPI0 SS, and EVSYS EVOUTA.
6 PC0 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions USART1 TxD, SPI0 MOSI, TCA0 WO0, and TCB0 output.
7 PC1 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions USART1 RxD, SPI0 MISO, TCA0 WO1, and TCB3 output.
8 PC2 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions TWI0 SDA (host), USART1 XCK, SPI0 SCK, TCA0 WO2, and EVSYS EVOUTC.
9 PC3 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions TWI0 SCL (host), USART1 XDIR, SPI0 SS, and TCA0 WO3.
10 PD0 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN0, TCA0 WO0, and CCL LUT2 input.
11 PD1 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN1, AC0 P3, TCA0 WO1, and CCL LUT2 input.
12 PD2 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN2, AC0 P0, TCA0 WO2, and EVSYS EVOUTD.
13 PD3 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN3, AC0 N0, TCA0 WO3, and CCL LUT2 output.
14 PD4 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN4, AC0 P1, and TCA0 WO4.
15 PD5 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN5, AC0 N1, and TCA0 WO5.
16 PD6 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions ADC0 AIN6, AC0 P2, and CCL LUT2 output.
17 PD7 bidirectional General-purpose I/O pin on the AVDD power domain with alternate functions VREFA, ADC0 AIN7, AC0 N2, and EVSYS EVOUTD.
18 AVDD power_in Analog supply pin for the ADC, analog comparator and the AVDD power domain pins.
19 GND power_in Ground pin.
20 PF0 bidirectional General-purpose I/O pin with alternate functions TOSC1 (32.768 kHz crystal), USART2 TxD, TCA0 WO0, and CCL LUT3 input.
21 PF1 bidirectional General-purpose I/O pin with alternate functions TOSC2 (32.768 kHz crystal), USART2 RxD, TCA0 WO1, and CCL LUT3 input.
22 PF2 bidirectional General-purpose I/O pin with alternate functions ADC0 AIN12, TWI0 SDA (client), USART2 XCK, TCA0 WO2, and EVSYS EVOUTF.
23 PF3 bidirectional General-purpose I/O pin with alternate functions ADC0 AIN13, TWI0 SCL (client), USART2 XDIR, TCA0 WO3, and CCL LUT3 output.
24 PF4 bidirectional General-purpose I/O pin with alternate functions ADC0 AIN14, USART2 TxD, and TCA0 WO4.
25 PF5 bidirectional General-purpose I/O pin with alternate functions ADC0 AIN15, USART2 RxD, and TCA0 WO5.
26 PF6 (RESET) input General-purpose I/O pin PF6, which can be configured as the external RESET pin, with USART2 XCK and CCL LUT3 output as alternate functions.
27 UPDI bidirectional Unified Program and Debug Interface pin used for programming and debugging.
28 VDD power_in Main supply pin for the VDD power domain.
29 GND power_in Ground pin.
30 PA0 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions EXTCLK, USART0 TxD, TCA0 WO0, and CCL LUT0 input.
31 PA1 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions USART0 RxD, TCA0 WO1, and CCL LUT0 input.
32 PA2 bidirectional General-purpose I/O pin on the VDD power domain with alternate functions TWI0 SDA (host), USART0 XCK, TCA0 WO2, TCB0 output, EVSYS EVOUTA, and CCL LUT0 input.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-32-EP(5x5)
Category Single Chip Microcomputer/Microcontroller
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 1.8 5.5 V Ordering information, ATmega4808-MUR, 32 VQFN, 20 MHz 521
Temperature range -40 85 °C Ordering information, ATmega4808-MUR, temperature range -40°C to +85°C 521
Max CPU speed 20 MHz Ordering information, ATmega4808-MUR, 1.8-5.5V supply 521

CAD (KiCad official)

  • Symbol: ATMEGA4808-MUR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: atmega4808-mur-etched.step / atmega4808-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega4808-mur.step / atmega4808-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (560 pp, sha256 a1755e46625fa50b, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF