component
NCL30059BDR2G
Public Made by Adomby adom
onsemi LED Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCL30059BDR2G
onsemi · LED Drivers · SOIC-8
NCL30059BDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supplies the driver, which accepts up to 16 V as limited by the internal zener clamp (VCC clamp 15.4 to 17.5 V at 20 mA). |
| 2 | Rt | input | Timing resistor pin; a resistor between this pin and GND sets the operating frequency, with Rt pin voltage limited to -0.3 to 5 V. |
| 3 | BO | input | Brown-out pin that detects low input voltage conditions and fully latches off the driver when brought above Vlatch (2 V typical). |
| 4 | GND | power_in | IC ground reference for the controller and the zener clamp connected between VCC and GND. |
| 5 | Mlower | output | Low-side driver output that drives the lower side MOSFET, with low-side output voltage limited to -0.3 V to VCC + 0.3 V. |
| 6 | HB | passive | Half-bridge connection that connects to the half-bridge output; the high-voltage bridge pin is rated -1 to +600 V. |
| 7 | Mupper | output | High-side driver output that drives the higher side MOSFET, referenced to the bridge pin (Vbridge - 0.3 V to Vboot + 0.3 V). |
| 8 | Vboot | power_in | Bootstrap pin and floating supply terminal for the upper stage, with floating supply voltage (Vboot - Vbridge) rated 0 to 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | LED Drivers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Turn-On Threshold Level, VCC Going Up | VCCON | 10 | 11 | 12 | V | 5 | |
| Minimum Operating Voltage after Turn-On | VCCmin | 8 | 9 | 10 | V | 5 | |
| Startup Voltage on the Floating Section | VbootON | 7.8 | 8.8 | 9.8 | V | 5 | |
| Cutoff Voltage on the Floating Section | Vbootmin | 7 | 8 | 9 | V | 5 | |
| Startup Current | ICC | 50 | A | VCC < VCCON, 0°C to +125°C Tamb | 5 | ||
| Startup Current | ICC | 65 | A | VCC < VCCON, -40°C to 0°C Tamb | 5 | ||
| Consumption During PFC Delay Period | ICC4 | 400 | A | 0°C to +125°C Tamb | 5 | ||
| Consumption During PFC Delay Period | ICC4 | 470 | A | -40°C to 0°C Tamb | 5 | ||
| VCC Zener Clamp Voltage | VCCclamp | 15.4 | 16 | 17.5 | V | @ 20 mA | 5 |
| Minimum Switching Frequency | FSW min | 24.25 | 25 | 25.75 | kHz | Rt = 35 k on Pin 2, DT = 600 ns | 5 |
| Maximum Switching Frequency | FSW max | 208 | 245 | 282 | kHz | Rt = 3.5 k on Pin 2, DT = 600 ns | 5 |
| Reference Voltage for all Current Generations | Vref RT | 3.33 | 3.5 | 3.67 | V | 5 | |
| Operating Duty Cycle Symmetry | DC | 48 | 50 | 52 | % | 5 | |
| Dead-Time (Measured Between 50% of Rise and Fall Edge) | T_dead | 540 | 610 | 720 | ns | 5 | |
| Leakage Current on High Voltage Pins to GND | IHV_Leak | 5 | A | 600 Vdc | 5 | ||
| Brown-Out Level | VBO | 0.95 | 1 | 1.05 | V | 5 | |
| Hysteresis Current, Vpin3 < VBO | IBO | 15.6 | 18.2 | 20.7 | A | Vpin3 < VBO | 5 |
| Latching Voltage on BO Pin | Vlatch | 1.9 | 2 | 2.1 | V | 5 | |
| Temperature Shutdown | TSD | 140 | °C | Guaranteed by design | 5 | ||
| High Voltage Bridge Pin (Pin 6) | Vbridge | -1 | 600 | V | 4 | ||
| Floating Supply Voltage | Vboot - Vbridge | 0 | 20 | V | 4 | ||
| High-Side Output Voltage | VDRV_HI | -0.3 | 0.3 | V | Min relative to Vbridge, max relative to Vboot (printed as Vbridge - 0.3 to Vboot + 0.3) | 4 | |
| Low-Side Output Voltage | VDRV_LO | -0.3 | 0.3 | V | Relative to VCC (printed as -0.3 to VCC +0.3) | 4 | |
| Allowable Output Slew Rate | dVbridge/dt | 50 | V/ns | 4 | |||
| Maximum Current that Can Flow into VCC Pin (Pin 1) | ICC | 20 | mA | 4 | |||
| Rt Pin Voltage | V_Rt | -0.3 | 5 | V | 4 | ||
| Maximum Voltage, All Pins | -0.3 | 10 | V | Except Pins 4 and 5 | 4 | ||
| Storage Temperature Range | -60 | 150 | °C | 4 | |||
| ESD Capability, Human Body Model | 2 | kV | All pins except pins 1, 6, 7 and 8 | 4 | |||
| ESD Capability, Machine Model | 200 | V | All pins except pins 1, 6, 7 and 8 | 4 | |||
| Thermal Resistance Junction-to-Air, IC Soldered on 50 mm2 Copper 35 µm | RJA | 178 | °C/W | IC soldered on 50 mm2 copper, 35 µm | 4 | ||
| Thermal Resistance Junction-to-Air, IC Soldered on 200 mm2 Copper 35 µm | RJA | 147 | °C/W | IC soldered on 200 mm2 copper, 35 µm | 4 |
CAD (KiCad official)
- Symbol:
NCL30059BDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncl30059bdr2g-etched.step/ncl30059bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncl30059bdr2g.step/ncl30059bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (16 pp, sha256
821dd396410c32f0, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).