A4982SETTR-T from Allegro MicroSystems, LLC, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT2B	output	DMOS full-bridge 2 output B driving the phase-2 motor winding; motor outputs are rated -2.0 to 37 V with output current limited to ±2 A.
2	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
3	VBB2	power_in	Load supply for full-bridge 2, operating range 8 to 35 V (35 V absolute maximum).
4	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
5	ENABLE	input	Active-low logic input; logic high disables all FET outputs, while logic low lets the internal control enable the outputs as required.
6	GND	power_in	Ground pin that must be tied externally to the exposed-pad ground plane under the device.
7	CP1	passive	Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
8	CP2	passive	Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
9	VCP	power_out	Charge pump reservoir terminal for high-side FET gate supply; a 0.1 µF ceramic capacitor is required between VCP and VBB.
10	VREG	power_out	Internally generated regulator output (nominal 7 V) for the sink-side FET gates; decouple with a 0.22 µF ceramic capacitor to ground.
11	MS1	input	Microstep select logic input (with internal 100 kΩ pull-down) that sets step resolution together with MS2.
12	MS2	input	Microstep select logic input (with internal 33.3 kΩ pull-down) that sets step resolution together with MS1.
13	RESET	input	Active-low logic input; low sets the translator to the Home state and turns off all FET outputs, and STEP inputs are ignored until it returns high.
14	ROSC	input	Fixed off-time timing pin: tie to VDD or GND for a 30 µs off-time, or tie through a resistor to ground where tOFF ≈ ROSC/825 µs.
15	SLEEP	input	Active-low logic input; logic low places the device in Sleep mode (<10 µA) disabling the output FETs, current regulator and charge pump, and a 1 ms delay is required after leaving Sleep before a STEP command.
16	VDD	power_in	Logic supply, operating range 3.0 to 5.5 V, with internal UVLO at about 2.8 V (rising).
17	STEP	input	Logic input; each low-to-high transition advances the motor one microstep, with minimum HIGH and LOW pulse widths of 1 µs.
18	REF	input	Transconductance reference voltage input, 0 to 4 V, that sets the maximum trip current as ITripMAX = VREF/(8×RS).
19	GND	power_in	Ground pin that must be tied externally to the exposed-pad ground plane under the device.
20	DIR	input	Logic input setting the direction of motor rotation; changes take effect only on the next STEP rising edge.
21	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
22	VBB1	power_in	Load supply for full-bridge 1, operating range 8 to 35 V (35 V absolute maximum).
23	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
24	OUT1B	output	DMOS full-bridge 1 output B driving the phase-1 motor winding; motor outputs are rated -2.0 to 37 V with output current limited to ±2 A.
25	SENSE1	passive	Sense resistor terminal for bridge 1; the SENSE1 voltage must not exceed the 0.5 V maximum rating (VSENSE -0.5 to 0.5 V).
26	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
27	OUT1A	output	DMOS full-bridge 1 output A driving the phase-1 motor winding; motor outputs are rated -2.0 to 37 V with output current limited to ±2 A.
28	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
29	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
30	OUT2A	output	DMOS full-bridge 2 output A driving the phase-2 motor winding; motor outputs are rated -2.0 to 37 V with output current limited to ±2 A.
31	NC	unconnected	No connection; the ET package adds this pin between critical output, sense and supply pins for no-smoke-no-fire compliance.
32	SENSE2	passive	Sense resistor terminal for bridge 2; the SENSE2 voltage must not exceed the 0.5 V maximum rating (VSENSE -0.5 to 0.5 V).
33	PAD	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	QFN-32-EP(5x5)
Category	Power Supply Chip
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Load Supply Voltage	VBB			35	V		2
Output Current	IOUT	-2		2	A		2
Logic Input Voltage	VIN	-0.3		5.5	V		2
Logic Supply Voltage	VDD	-0.3		5.5	V		2
Motor Outputs Voltage		-2		37	V		2
Sense Voltage	VSENSE	-0.5		0.5	V		2
Reference Voltage	VREF			5.5	V		2
Operating Ambient Temperature, Range S	TA	-20		85	ºC		2
Maximum Junction Temperature	TJ(max)			150	ºC		2
Storage Temperature	Tstg	-55		150	ºC		2
Load Supply Voltage Range, Operating	VBB	8		35	V	Operating	4
Load Supply Voltage Range, During Sleep Mode	VBB	0		35	V	During Sleep Mode	4
Logic Supply Voltage Range, Operating	VDD	3		5.5	V	Operating	4
Output On Resistance, Source Driver	RDSON		320	430	mΩ	Source Driver, IOUT = -1.5 A	4
Output On Resistance, Sink Driver	RDSON		320	430	mΩ	Sink Driver, IOUT = 1.5 A	4
Body Diode Forward Voltage, Source Diode	VF			1.3	V	Source Diode, IF = -1.5 A	4
Body Diode Forward Voltage, Sink Diode	VF			1.3	V	Sink Diode, IF = 1.5 A	4
Motor Supply Current	IBB			4	mA	fPWM < 50 kHz	4
Motor Supply Current, Operating Outputs Disabled	IBB			2	mA	Operating, outputs disabled	4
Motor Supply Current, Sleep Mode	IBB			10	μA	Sleep Mode	4
Logic Supply Current	IDD			8	mA	fPWM < 50 kHz	4
Logic Supply Current, Outputs Off	IDD			5	mA	Outputs off	4
Logic Supply Current, Sleep Mode	IDD			10	μA	Sleep Mode	4
Logic Input Current, Logic High	IIN(1)	-20		20	µA	VIN = VDD×0.7	4
Logic Input Current, Logic Low	IIN(0)	-20		20	µA	VIN = VDD×0.3	4
Logic Input Hysteresis	VHYS(IN)	5	11	19	%	As a % of VDD	4
Blank Time	tBLANK	0.7	1	1.3	μs		4
Fixed Off-Time	tOFF	20	30	40	μs	OSC = VDD or GND	4
Fixed Off-Time	tOFF	23	30	37	μs	ROSC = 25 kΩ	4
Reference Input Voltage Range	VREF	0		4	V		4
Reference Input Current	IREF	-3	0	3	µA		4
Current Trip-Level Error	errI	-15		15	%	VREF = 2 V, %ITripMAX = 38.27%	4
Current Trip-Level Error	errI	-5		5	%	VREF = 2 V, %ITripMAX = 70.71%	4
Crossover Dead Time	tDT	100	475	800	ns		4
Overcurrent Protection Threshold	IOCPST	2.1			A		4
VDD Undervoltage Lockout, Rising	VDDUVLO	2.7	2.8	2.9	V	VDD rising	4
Package Thermal Resistance (ET package)	RθJA		32		ºC/W	ET package; estimated, on 4-layer PCB, based on JEDEC standard; still air	5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	exposed pads for enhanced thermal dissipation and are lead (Pb) free (suffix -T), with 100% matte tin plated leadframes.	2

CAD (KiCad official)

Symbol: A4982SETTR-T
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: a4982settr-t-etched.step / a4982settr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4982settr-t.step / a4982settr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (20 pp, sha256 7c370c2d4c680549, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A4982SETTR-T

Verified A4982SETTR-T

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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