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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

ATSAME70J21A-AN

Microchip Tech · Pre-ordered MCUs · LQFP-64(10x10)

ATSAME70J21A-AN from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PD0	bidirectional	PIO line PD0 with DAC1 (analog output, selected when DACC_CHER.CH1 is set), GTXCK, PWMC1_PWML0, SPI1_NPCS1 and DCD0 alternate functions.
2	PD31	bidirectional	PIO line PD31 with QIO3 Quad SPI data, UTXD3, PCK2 and ISI_D11 alternate functions.
3	VDDOUT	power_out	Voltage regulator output that supplies the core, which must be decoupled with 100 nF and 1 uF capacitors.
4	VDDIN	power_in	Voltage regulator input that also supplies the AFE, DAC and analog comparator, and must be at the same level as VDDIO.
5	VREFP	power_in	Reference voltage for the AFE and DAC, which must rise simultaneously with VDDIO and VDDIN at power-up.
6	GND	power_in	Ground reference for the device.
7	PB1	bidirectional	PIO line PB1 with AFE1_AD0/RTCOUT1 analog input or RTC output, PWMC0_PWMH1, GTSUCOMP, TXD0 and TK alternate functions.
8	PB0	bidirectional	PIO line PB0 with AFE0_AD10/RTCOUT0 analog input or RTC output, PWMC0_PWMH0, RXD0 and TF alternate functions.
9	PB2	bidirectional	PIO line PB2 with AFE0_AD5 analog input, CANTX0, CTS0 and SPI0_NPCS0 alternate functions.
10	VDDIO	power_in	Supplies the peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads, and must be 3.0V to 3.6V for USB operations.
11	PB3	bidirectional	PIO line PB3 with AFE0_AD2/WKUP12 analog input or wakeup input, CANRX0, PCK2, RTS0 and ISI_D2 alternate functions.
12	PA21	bidirectional	PIO line PA21 with AFE0_AD1/PIODCEN2 analog input, RXD1, PCK1 and PWMC1_PWMFI0 alternate functions.
13	VDDCORE	power_in	Supplies the core, embedded memories and peripherals, and must not be above VDDIN or VDDIO.
14	GND	power_in	Ground reference for the device.
15	PA7	bidirectional	PIO line PA7 used as XIN32, the 32.768 kHz crystal oscillator input or bypass clock input, with PWMC0_PWMH3 as alternate function.
16	PA8	bidirectional	PIO line PA8 used as XOUT32, the 32.768 kHz crystal oscillator output, with PWMC1_PWMH3 and AFE0_ADTRG as alternate functions.
17	PA22	bidirectional	PIO line PA22 with PIODCCLK parallel capture clock input, RK clock and PWMC0_PWMEXTRG1 alternate functions.
18	PA13	bidirectional	PIO line PA13 with PIODC7 parallel capture data input, QIO0 Quad SPI data and PWMC0_PWMH2 alternate functions.
19	PA14	bidirectional	PIO line PA14 with WKUP8/PIODCEN1 wakeup or capture enable input, QSCK Quad SPI clock and PWMC0_PWMH3 alternate functions.
20	PD25	bidirectional	PIO line PD25 with PWMC0_PWML1, SPI0_NPCS1, URXD2 and ISI_VSYNC alternate functions.
21	PD26	bidirectional	PIO line PD26 with PWMC0_PWML2, TDO, UTXD2 and UTXD1 alternate functions.
22	PD24	bidirectional	PIO line PD24 with PWMC0_PWML0, RF, TCLK11 and ISI_HSYNC alternate functions.
23	PA24	bidirectional	PIO line PA24 with RTS1, PWMC0_PWMH1, A20 address output and ISI_PCK alternate functions.
24	VDDCORE	power_in	Supplies the core, embedded memories and peripherals, and must not be above VDDIN or VDDIO.
25	PD22	bidirectional	PIO line PD22 with PWMC0_PWMH2, TIOB11, ISI_D0 and SPI0_SPCK related alternate functions as printed in the table.
26	PD21	bidirectional	PIO line PD21 with PWMC0_PWMH1, TIOA11 and ISI_D1 alternate functions.
27	PA11	bidirectional	PIO line PA11 with WKUP7/PIODC5 wakeup or capture input, QCS Quad SPI chip select, PWMC0_PWMH0 and PWMC1_PWML0 alternate functions.
28	PA10	bidirectional	PIO line PA10 with PIODC4 parallel capture input, UTXD0, PWMC0_PWMEXTRG0 and RD alternate functions.
29	PA12	bidirectional	PIO line PA12 with PIODC6 parallel capture input, QIO1 Quad SPI data, PWMC0_PWMH1 and PWMC1_PWMH0 alternate functions.
30	PA27	bidirectional	PIO line PA27 with DTR1, TIOB2 and ISI_D7 alternate functions.
31	GND	power_in	Ground reference for the device.
32	PA5	bidirectional	PIO line PA5 with WKUP4/PIODC2 wakeup or capture input, PWMC1_PWML3, ISI_D4 and URXD1 alternate functions.
33	PA9	bidirectional	PIO line PA9 with WKUP6/PIODC3 wakeup or capture input, URXD0, ISI_D3 and PWMC0_PWMFI0 alternate functions.
34	PA4	bidirectional	PIO line PA4 with WKUP3/PIODC1 wakeup or capture input, TWCK0, TCLK0 and UTXD1 alternate functions.
35	PB6	bidirectional	PIO line PB6 used as SWDIO/TMS serial wire data or test mode select, which is a Schmitt trigger input with no internal pull-up at reset.
36	NRST	bidirectional	Microcontroller reset input/output, active low, with internal pull-up.
37	TST	input	Test select input, which has an internal pull-down of about 15 kOhm to GND for normal operation.
38	PB12	bidirectional	PIO line PB12 used as ERASE input for Flash erase mode, which must be low at startup when not used, with PWMC0_PWML1, GTSUCOMP and PCK0 alternate functions.
39	PB7	bidirectional	PIO line PB7 used as SWCLK/TCK serial wire clock or test clock, which is a Schmitt trigger input.
40	PA3	bidirectional	PIO line PA3 with PIODC0 parallel capture input, TWD0, LONCOL1 and PCK2 alternate functions.
41	PD12	bidirectional	PIO line PD12 with GRX3 Ethernet receive data, CANTX1 related output and ISI_D6 alternate functions.
42	VDDIO	power_in	Supplies the peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads, and must be 3.0V to 3.6V for USB operations.
43	PD11	bidirectional	PIO line PD11 with GRX2 Ethernet receive data, PWMC0_PWMH0, GTSUCOMP and ISI_D5 alternate functions.
44	PD10	bidirectional	PIO line PD10 with GCRS Ethernet carrier sense, PWMC0_PWML0, TDO and MLBSIG alternate functions, with a pull-down at reset.
45	JTAGSEL	input	JTAG selection input, which when high selects JTAG boundary scan and has an internal pull-down of about 15 kOhm to GND.
46	PB4	bidirectional	PIO line PB4 used as TDI test data input, with TWD1, PWMC0_PWMH2, MLBCLK and TXD1 alternate functions.
47	PB5	bidirectional	PIO line PB5 used as TDO/TRACESWO test data or trace output, with WKUP13, TWCK1, PWMC0_PWML0 and MLBDAT alternate functions.
48	PD9	bidirectional	PIO line PD9 with GMDIO Ethernet management data, PWMC0_PWMFI2 and AFE1_ADTRG alternate functions.
49	PD8	bidirectional	PIO line PD8 with GMDC Ethernet management clock, PWMC0_PWMFI1 and TRACECLK trace clock alternate functions.
50	PD7	bidirectional	PIO line PD7 with GRXER Ethernet receive error, PWMC1_PWMH3 and TRACED3 trace data alternate functions.
51	PD6	bidirectional	PIO line PD6 with GRX1 Ethernet receive data, PWMC1_PWML3 and TRACED2 trace data alternate functions.
52	VDDPLL	power_in	Supplies PLLA and the fast RC oscillator, which is noise sensitive and needs careful decoupling.
53	PD5	bidirectional	PIO line PD5 with GRX0 Ethernet receive data, PWMC1_PWMH2 and TRACED1 trace data alternate functions.
54	PD4	bidirectional	PIO line PD4 with GRXDV Ethernet receive data valid, PWMC1_PWML2 and TRACED0 trace data alternate functions.
55	PD3	bidirectional	PIO line PD3 with GTX1 Ethernet transmit data, PWMC1_PWMH1, UTXD4 and RI0 alternate functions.
56	PD2	bidirectional	PIO line PD2 with GTX0 Ethernet transmit data, PWMC1_PWML1, DSR0 and SPI1_NPCS3 alternate functions.
57	PD1	bidirectional	PIO line PD1 with GTXEN Ethernet transmit enable, PWMC1_PWMH0, SPI1_NPCS2 and DTR0 alternate functions.
58	VDDIO	power_in	Supplies the peripheral I/O lines, backup part, 1 Kbyte backup SRAM, 32 kHz oscillator and oscillator pads, and must be 3.0V to 3.6V for USB operations.
59	DM	bidirectional	USB high-speed data minus line of the USBHS device or host interface, powered from VDDUTMII.
60	DP	bidirectional	USB high-speed data plus line of the USBHS device or host interface, powered from VDDUTMII.
61	VDDCORE	power_in	Supplies the core, embedded memories and peripherals, and must not be above VDDIN or VDDIO.
62	PB8	bidirectional	PIO line PB8 used as XOUT, the main crystal oscillator output, with its direction set by the PIO configuration.
63	PB9	bidirectional	PIO line PB9 used as XIN, the main crystal oscillator input, with its direction set by the PIO configuration.
64	VDDPLLUSB	power_in	Supplies the UTMI PLL and the 3 MHz to 20 MHz oscillator, which is noise sensitive.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Single supply voltage		1.7		3.6	V	Industrial temperature devices	2

CAD (KiCad official)

Symbol: ATSAME70J21A-AN
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: atsame70j21a-an-etched.step / atsame70j21a-an-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsame70j21a-an.step / atsame70j21a-an.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (1943 pp, sha256 94ed9d6997caca1c, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF