ADUM321N0BRZ from ADI(亚德诺), in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator side 1 (2.25 V to 5.5 V operation); requires a 0.1 µF bypass capacitor.
2	VOA	output	Logic output A.
3	VIB	input	Logic input B.
4	GND1	power_in	Ground reference for isolator side 1.
5	GND2	power_in	Ground reference for isolator side 2.
6	VOB	output	Logic output B.
7	VIA	input	Logic input A.
8	VDD2	power_in	Supply voltage for isolator side 2 (2.25 V to 5.5 V operation); requires a 0.1 µF bypass capacitor.

Key specifications

Parameter	Value
Manufacturer	ADI(亚德诺)
Package	SOIC-8
Category
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating Temperature	TA	-40		125	°C		13
Supply Voltage VDD1	VDD1	2.25		5.5	V		13
Supply Voltage VDD2	VDD2	2.25		5.5	V		13
Input Signal Rise and Fall Times				1	ms		13
Supply Voltage VDD1 to GND1	VDD1	-0.5		7	V	TA = 25°C	14
Supply Voltage VDD2 to GND2	VDD2	-0.5		7	V	TA = 25°C	14
Input Voltages (VIA, VIB)		-0.5			V	Upper limit printed as VDDI1 + 0.5 V	14
Output Voltages (VOA, VOB)		-0.5			V	Upper limit printed as VDDO2 + 0.5 V	14
Average Output Current per Pin, Side 1	IO1	-10		10	mA	TA = 25°C	14
Average Output Current per Pin, Side 2	IO2	-10		10	mA	TA = 25°C	14
Common-Mode Transients		-300		300	kV/µs	Across the insulation barrier	14
Storage Temperature Range	TST	-65		150	°C		14
Ambient Operating Temperature Range	TA	-40		125	°C		14
Data Rate (5 V)		150			Mbps	Within PWD limit	4
Propagation Delay (5 V)	tPHL, tPLH		6.2	10	ns	50% input to 50% output	4
Pulse Width Distortion (5 V)	PWD		0.3	3	ns	/tPLH − tPHL/	4
Propagation Delay Skew (5 V)	tPSK			6.1	ns	Between any two units at the same temperature, voltage, and load	4
Channel Matching, Codirectional (5 V)	tPSKCD		0.3	3	ns		4
Channel Matching, Opposing Direction (5 V)	tPSKOD		0.3	3	ns		4
Input Threshold Logic High (5 V)	VIH	0.7			× VDDx	Printed as 0.7 × VDDx	4
Input Threshold Logic Low (5 V)	VIL			0.3	× VDDx	Printed as 0.3 × VDDx	4
Output Voltage Logic Low (5 V)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	4
Output Voltage Logic Low (5 V)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	4
Input Current per Channel (5 V)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx	4
Quiescent Supply Current IDD1 (5 V)	IDD1 (Q)		0.63	1	mA	VI = 0 (N0)	4
Quiescent Supply Current IDD2 (5 V)	IDD2 (Q)		0.63	1	mA	VI = 0 (N0)	4
Quiescent Supply Current IDD1 (5 V)	IDD1 (Q)		2.66	3.8	mA	VI = 1 (N0)	4
Quiescent Supply Current IDD2 (5 V)	IDD2 (Q)		2.68	3.8	mA	VI = 1 (N0)	4
Positive VDDx UVLO Threshold	VDDxUV+		2	2.2	V	Rising supply voltage enable threshold	5
Negative VDDx UVLO Threshold	VDDxUV−		1.7	1.8	V	Falling supply voltage lockout threshold	5
Common-Mode Transient Immunity, High (5 V)	/CMH/	100	180		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	5
Common-Mode Transient Immunity, Low (5 V)	/CML/	100	180		kV/µs	VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V	5
Data Rate (3.3 V)		100			Mbps	Within PWD limit	6
Propagation Delay (3.3 V)	tPHL, tPLH		6.6	10	ns	50% input to 50% output	6
Pulse Width Distortion (3.3 V)	PWD		0.5	3	ns	/tPLH − tPHL/	6
Propagation Delay Skew (3.3 V)	tPSK			7.5	ns	Between any two units at the same temperature, voltage, and load	6
Channel Matching, Codirectional (3.3 V)	tPSKCD		0.5	3	ns		6
Channel Matching, Opposing Direction (3.3 V)	tPSKOD		0.5	3	ns		6
Input Current per Channel (3.3 V)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx	6
Quiescent Supply Current IDD1 (3.3 V)	IDD1 (Q)		0.61	0.9	mA	VI = 0 (N0)	6
Quiescent Supply Current IDD2 (3.3 V)	IDD2 (Q)		0.61	0.9	mA	VI = 0 (N0)	6
Quiescent Supply Current IDD1 (3.3 V)	IDD1 (Q)		2.6	3.7	mA	VI = 1 (N0)	7
Quiescent Supply Current IDD2 (3.3 V)	IDD2 (Q)		2.6	3.7	mA	VI = 1 (N0)	7
Data Rate (2.5 V)		100			Mbps	Within PWD limit	8
Propagation Delay (2.5 V)	tPHL, tPLH		7.2	14	ns	50% input to 50% output	8
Pulse Width Distortion (2.5 V)	PWD		0.3	4.5	ns	/tPLH − tPHL/	8
Propagation Delay Skew (2.5 V)	tPSK			8.9	ns	Between any two units at the same temperature, voltage, and load	8
Channel Matching, Codirectional (2.5 V)	tPSKCD		0.4	5	ns		8
Channel Matching, Opposing Direction (2.5 V)	tPSKOD		0.4	5	ns		8
Input Current per Channel (2.5 V)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	8
Quiescent Supply Current IDD1 (2.5 V)	IDD1 (Q)		0.6	0.9	mA	VI = 0 (N0)	9
Quiescent Supply Current IDD2 (2.5 V)	IDD2 (Q)		0.6	0.9	mA	VI = 0 (N0)	9
Quiescent Supply Current IDD1 (2.5 V)	IDD1 (Q)		2.6	3.7	mA	VI = 1 (N0)	9
Quiescent Supply Current IDD2 (2.5 V)	IDD2 (Q)		2.6	3.7	mA	VI = 1 (N0)	9
Junction-to-Ambient Thermal Resistance SOIC_N (R-8)	θJA		92.96		°C/W	JEDEC 2S2P board, no vias, still air (simulated)	14
Junction-to-Board Thermal Resistance SOIC_N (R-8)	θJB		177.75		°C/W	JEDEC 2S2P board, no vias, still air (simulated)	14
Junction-to-Board Characterization Parameter SOIC_N (R-8)	ΨJB		62.66		°C/W	JEDEC 2S2P board, no vias, still air (simulated)	14
Junction-to-Top Characterization Parameter SOIC_N (R-8)	ΨJT		7.07		°C/W	JEDEC 2S2P board, no vias, still air (simulated)	14
Output Rise/Fall Time (5 V)	tR/tF		2.5		ns	10% to 90%	5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pet		IEC 60747-17 (REINFORCED INSULATION) Maximum Repetitive Peak Isolation Voltage VIORM 636 V peak	10

CAD (KiCad official)

Symbol: ADUM321N0BRZ
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: adum321n0brz-etched.step / adum321n0brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum321n0brz.step / adum321n0brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ADI(亚德诺) datasheet (22 pp, sha256 0c66291bb572c2fe, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADUM321N0BRZ

Verified ADUM321N0BRZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README