component
UCC28C57HDR
Public Made by Adomby adom
Texas Instruments , SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownUCC28C57HDR
Texas Instruments · IC · SOIC-8
UCC28C57HDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation that can both source and sink current, is internally current-limited, and lets the user command zero duty cycle by externally forcing COMP to GND. |
| 2 | FB | input | Inverting input of the error amplifier, whose noninverting reference is internally trimmed to 2.5 V ±1%, used to close the voltage-feedback loop for stability. |
| 3 | CS | input | Primary-side current-sense input to the PWM comparator that terminates OUT conduction when it reaches the error-amplifier-derived threshold, connected to the current-sense resistor. |
| 4 | RT/CT | bidirectional | Oscillator set point where timing resistor RRT connects to VREF and timing capacitor CCT connects to GND; on the UCC28C57H the switching frequency is one-half of fOSC. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic-level controller section, to which all device voltages are referenced. |
| 6 | OUT | output | Totem-pole drive output for directly driving a MOSFET with up to 1 A peak source and sink; on the UCC28C57H it switches at one-half the oscillator frequency, limiting maximum duty cycle to below 50%, and it is held low when VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply input with an absolute maximum of 30 V, requiring a bypass capacitor of typically 0.1 µF connected directly to GND with minimal trace length. |
| 8 | VREF | power_out | 5-V reference output (±1% tolerance for the UCC28C5x family) that requires a ceramic bypass of at least 0.1 µF to GND placed close to the pin and must not have external voltages above the specified VREF superimposed on it. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VDD recommended | VVDD | 28 | V | 6 | |||
| Output driver voltage recommended | VOUT | 28 | V | 6 | |||
| Average output driver current | IOUT | 200 | mA | 6 | |||
| Reference output current | IOUT(VREF) | -20 | mA | 6 | |||
| Operating junction temperature (UCC28C5x) | TJ | -40 | 125 | °C | UCC28C5x | 6 | |
| Input voltage VDD | VDD | 30 | V | 5 | |||
| Input current IVDD | IVDD | 30 | mA | 5 | |||
| Output drive current (peak) | -1 | 1 | A | 5 | |||
| Output energy (capacitive load) | EOUT | 5 | µJ | 5 | |||
| Analog input voltage COMP, CS, FB, RT/CT | -0.3 | 6.3 | V | 5 | |||
| Output driver voltage OUT | -0.3 | 30 | V | 5 | |||
| Reference voltage VREF | VREF | 7 | V | 5 | |||
| Error amplifier output sink current COMP | 10 | mA | 5 | ||||
| Total power dissipation, D package (as printed) | 72.3 | °C/W | TA = 25°C | 5 | |||
| Lead temperature (soldering, 10 s) | TLEAD | 300 | °C | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| VREF voltage, initial accuracy | VVREF | 4.95 | 5 | 5.05 | V | TJ = 25°C, IOUT = 1 mA | 7 |
| Total output variation (VREF) | 4.85 | 5.15 | V | 7 | |||
| Output short circuit (source current) VREF | IVREF | 30 | 45 | 55 | mA | 7 | |
| Line regulation (VREF) | 0.2 | 20 | mV | 12 V ≤ VVDD ≤ 25 V | 7 | ||
| Load regulation (VREF) | 3 | 25 | mV | 1 mA to 20 mA | 7 | ||
| Temperature stability (VREF) | 0.2 | 0.4 | mV/°C | 7 | |||
| Long term stability (VREF) | 5 | 25 | mV | 1000 hours, TJ = 125°C | 7 | ||
| Oscillator initial accuracy | fOSC | 50.5 | 53 | 55 | kHz | TJ = 25°C | 7 |
| Oscillator voltage stability | 0.2 | 1 | % | 12 V ≤ VVDD ≤ 25 V | 7 | ||
| Oscillator temperature stability | 1 | 2.5 | % | TJ(MIN) to TJ(MAX) | 7 | ||
| Oscillator discharge current | 7.7 | 8.4 | 9 | mA | TJ = 25°C, VRT/CT = 2 V | 7 | |
| Oscillator discharge current | 7.2 | 8.4 | 9.5 | mA | VRT/CT = 2 V | 7 | |
| Feedback input voltage, initial accuracy | VFB | 2.475 | 2.5 | 2.525 | V | VCOMP = 2.5 V, TJ = 25°C | 7 |
| Feedback input voltage, total variation | VFB | 2.45 | 2.5 | 2.55 | V | VCOMP = 2.5 V | 7 |
| Input bias current (source current) error amplifier | IFB | 0.1 | 2 | µA | VFB = 5 V | 7 | |
| Open-loop voltage gain | AVOL | 65 | 90 | dB | 2 V ≤ VOUT ≤ 4 V | 7 | |
| Unity gain bandwidth | 1 | 1.5 | MHz | 7 | |||
| Output sink current | 2 | 14 | mA | VFB = 2.7 V, VCOMP = 1.1 V | 7 | ||
| Output source current | 0.5 | 1 | mA | VFB = 2.3 V, VCOMP = 5 V | 7 | ||
| Low-level COMP voltage | VOL | 0.1 | 1.1 | V | VFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF | 7 | |
| Current sense gain | ACS | 2.85 | 3 | 3.15 | V/V | 7 | |
| Maximum input signal (current sense) | VCS | 0.9 | 1 | 1.1 | V | VFB < 2.4 V | 7 |
| Input bias current (source current) current sense | ICS | 0.1 | 2 | µA | 7 | ||
| CS to output delay | tD | 35 | 70 | ns | 7 | ||
| RDS(on) pulldown (VOUT low) | VOUT(low) | 5.5 | 15 | Ω | ISINK = 200 mA | 7 | |
| RDS(on) pullup (VOUT high) | VOUT(high) | 10 | 25 | Ω | ISOURCE = 200 mA | 7 | |
| Rise time | tRISE | 25 | 50 | ns | TJ = 25°C, COUT = 1 nF | 7 | |
| Fall time | tFALL | 20 | 40 | ns | TJ = 25°C, COUT = 1 nF | 7 | |
| Start threshold (UCC28C57H) | VDDON | 17.6 | 18.8 | 20 | V | 8 | |
| Minimum operating voltage (UCC28C57H) | VDDOFF | 15 | 15.5 | 16 | V | 8 | |
| UVLO hysteresis (UCC28C57H) | VDDHyst | 2.6 | 3.3 | V | 8 | ||
| Maximum duty cycle (UCC28C57H) | DMAX | 47 | 48 | % | VFB < 2.4 V | 8 | |
| Start-up current | ISTART-UP | 50 | 75 | µA | VVDD = VDDON, 0.5 V | 8 | |
| Operating supply current | IVDD | 1.3 | 2 | mA | VFB = VCS = 0 V | 8 | |
| Junction-to-ambient thermal resistance (D, SOIC) | RθJA | 128.9 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance (D, SOIC) | RθJC(top) | 71.7 | °C/W | 6 | |||
| Junction-to-board thermal resistance (D, SOIC) | RθJB | 72.3 | °C/W | 6 | |||
| Junction-to-top characterization parameter (D, SOIC) | ψJT | 23.4 | °C/W | 6 | |||
| Junction-to-board characterization parameter (D, SOIC) | ψJB | 71.5 | °C/W | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | The inductor rising slope (Sn) at the CS pin is calculated with Equation 34. Sn = | 34 |
CAD (KiCad official)
- Symbol:
UCC28C57HDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28c57hdr-etched.step/ucc28c57hdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28c57hdr.step/ucc28c57hdr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (58 pp, sha256
d9b2cab289f0aa82, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).