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DRV8320RSRHAR

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Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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DRV8320RSRHAR

Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-40-EP(6x6)

DRV8320RSRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Device power ground; also serves as gate driver return path for low-side MOSFET; must be connected externally to AGND and BGND.
2 CPL power_in Charge pump switch node; connect X5R or X7R 47nF capacitor rated at VM between CPH and CPL.
3 CPH power_in Charge pump switch node; connect X5R or X7R 47nF capacitor rated at VM between CPH and CPL.
4 VCP power_in Charge pump output; connect X5R or X7R 1µF 25V capacitor between VCP and VM.
5 VM power_in Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with 0.1µF and ≥10µF capacitors to PGND.
6 VDRAIN input High-side MOSFET drain input; connects to common drain point of high-side MOSFETs and provides input to VDS monitor.
7 GHA output High-side gate driver output for phase A; drives high-side power MOSFET gate with up to 1A pull current.
8 SHA bidirectional High-side source pin for phase A; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output.
9 GLA output Low-side gate driver output for phase A; drives low-side power MOSFET gate with up to 2A sink current.
10 SLA input Low-side source input for phase A; connects to low-side MOSFET source and provides input to VDS monitor.
11 SLB input Low-side source input for phase B; connects to low-side MOSFET source and provides input to VDS monitor.
12 GLB output Low-side gate driver output for phase B; drives low-side power MOSFET gate with up to 2A sink current.
13 SHB bidirectional High-side source pin for phase B; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output.
14 GHB output High-side gate driver output for phase B; drives high-side power MOSFET gate with up to 1A pull current.
15 GHC output High-side gate driver output for phase C; drives high-side power MOSFET gate with up to 1A pull current.
16 SHC bidirectional High-side source pin for phase C; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output.
17 GLC output Low-side gate driver output for phase C; drives low-side power MOSFET gate with up to 2A sink current.
18 SLC input Low-side source input for phase C; connects to low-side MOSFET source and provides input to VDS monitor.
19 GND power_in Device ground; connects to system ground.
20 nFAULT tri_state Fault indicator output (open-drain); pulled low during fault conditions, requires external pull-up resistor to VCC.
21 SDO tri_state Serial data output (open-drain); outputs data on SCLK rising edge, requires external pull-up resistor.
22 SDI input Serial data input; data captured on SCLK falling edge for SPI communication.
23 SCLK input Serial clock input; controls timing for serial data transfers on falling and rising edges.
24 nSCS input Serial chip select (active low); logic low on this pin enables SPI interface communication.
25 ENABLE input Gate driver enable (active high); device enters sleep mode when low; 8µs to 40µs pulse resets faults without entering sleep.
26 AGND power_in Device analog ground; must be connected externally to BGND and PGND.
27 DVDD power_out 3.3V internal regulator output (30mA max); connect X5R or X7R 1µF 6.3V capacitor to AGND.
28 INHA input High-side gate driver control input for phase A; controls output in 6x PWM mode.
29 INLA input Low-side gate driver control input for phase A; controls output in 6x PWM mode.
30 INHB input High-side gate driver control input for phase B; controls output in 6x PWM mode.
31 INLB input Low-side gate driver control input for phase B; controls output in 6x PWM mode.
32 INHC input High-side gate driver control input for phase C; controls output in 6x PWM mode.
33 INLC input Low-side gate driver control input for phase C; controls output in 6x PWM mode.
34 BGND power_in Buck regulator ground; must be connected externally to AGND and PGND.
35 CB power_in Buck regulator bootstrap input; connect X5R or X7R 0.1µF 16V capacitor between CB and SW.
36 SW output Buck regulator switch node; connects to inductor, diode, and CB bootstrap capacitor in buck converter topology.
37 NC unconnected No internal connection; can be left floating or connected to system ground.
38 VIN power_in Buck regulator power supply input (4V to 60V); connect X5R or X7R capacitor rated at VM between VIN and BGND.
39 nSHDN input Buck regulator shutdown input (active low); high-voltage tolerant with internal pull-up; pull below 1.25V to disable.
40 FB input Buck regulator feedback input; resistor divider from output sets buck regulator output voltage.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Motor Driver ICs
Pins 41

CAD (KiCad official)

  • Symbol: DRV8320RSRHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: drv8320rsrhar-etched.step / drv8320rsrhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8320rsrhar.step / drv8320rsrhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (98 pp, sha256 9c4eee0ec7239000, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF