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STM32L151C8U6A
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L151C8U6A
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32L151C8U6A from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VLCD | power_in | LCD controller supply rail; the datasheet states this pin applies to STM32L152 devices only and must be connected to VDD on STM32L151 devices. |
| 2 | PC13-WKUP2 | bidirectional | 5 V tolerant (FT) I/O with alternate functions RTC_TAMP1, RTC_TS and RTC_OUT, and wakeup input WKUP2. |
| 3 | PC14-OSC32_IN | bidirectional | Standard 3.3 V (TC) I/O that is OSC32_IN when the LSE oscillator is on and can be used as PC14 GPIO when the LSE is off. |
| 4 | PC15-OSC32_OUT | bidirectional | Standard 3.3 V (TC) I/O that is OSC32_OUT when the LSE oscillator is on and can be used as PC15 GPIO when the LSE is off. |
| 5 | PH0-OSC_IN | bidirectional | Standard 3.3 V (TC) I/O that is OSC_IN when the HSE oscillator is on and can be used as PH0 GPIO when the HSE is off. |
| 6 | PH1-OSC_OUT | bidirectional | Standard 3.3 V (TC) I/O that is OSC_OUT when the HSE oscillator is on and can be used as PH1 GPIO when the HSE is off. |
| 7 | NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor. |
| 8 | VSSA | power_in | Analog ground pin for the analog supply domain. |
| 9 | VDDA | power_in | Analog supply pin for the analog blocks (ADC, DAC and comparators). |
| 10 | PA0-WKUP1 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART2_CTS, TIM2_CH1_ETR, ADC_IN0, COMP1_INP, wakeup WKUP1 and RTC_TAMP2. |
| 11 | PA1 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART2_RTS, TIM2_CH2, LCD_SEG0, ADC_IN1 and COMP1_INP. |
| 12 | PA2 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART2_TX, TIM2_CH3, TIM9_CH1, LCD_SEG1, ADC_IN2 and COMP1_INP. |
| 13 | PA3 | bidirectional | Standard 3.3 V (TC) I/O with alternate functions USART2_RX, TIM2_CH4, TIM9_CH2, LCD_SEG2, ADC_IN3 and COMP1_INP. |
| 14 | PA4 | bidirectional | Standard 3.3 V (TC) I/O with alternate functions SPI1_NSS, USART2_CK, ADC_IN4, DAC_OUT1 and COMP1_INP. |
| 15 | PA5 | bidirectional | Standard 3.3 V (TC) I/O with alternate functions SPI1_SCK, TIM2_CH1_ETR, ADC_IN5, DAC_OUT2 and COMP1_INP. |
| 16 | PA6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MISO, TIM3_CH1, LCD_SEG3, TIM10_CH1, ADC_IN6 and COMP1_INP. |
| 17 | PA7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MOSI, TIM3_CH2, LCD_SEG4, TIM11_CH1, ADC_IN7 and COMP1_INP. |
| 18 | PB0 | bidirectional | Standard 3.3 V (TC) I/O with alternate functions TIM3_CH3, LCD_SEG5, ADC_IN8, COMP1_INP, VREF_OUT and VLCDRAIL3. |
| 19 | PB1 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM3_CH4, LCD_SEG6, ADC_IN9, COMP1_INP and VREF_OUT. |
| 20 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O that also serves as the BOOT1 pin and the VLCDRAIL1 function. |
| 21 | PB10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C2_SCL, USART3_TX, TIM2_CH3 and LCD_SEG10. |
| 22 | PB11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C2_SDA, USART3_RX, TIM2_CH4 and LCD_SEG11. |
| 23 | VSS_1 | power_in | Ground pin of the digital supply domain. |
| 24 | VDD_1 | power_in | Digital power supply pin of the device. |
| 25 | PB12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_NSS, I2C2_SMBA, USART3_CK, LCD_SEG12, TIM10_CH1, ADC_IN18, COMP1_INP and VLCDRAIL2. |
| 26 | PB13 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_SCK, USART3_CTS, LCD_SEG13, TIM9_CH1, ADC_IN19 and COMP1_INP. |
| 27 | PB14 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MISO, USART3_RTS, LCD_SEG14, TIM9_CH2, ADC_IN20 and COMP1_INP. |
| 28 | PB15 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MOSI, LCD_SEG15, TIM11_CH1, ADC_IN21, COMP1_INP and RTC_REFIN. |
| 29 | PA8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_CK, MCO and LCD_COM0. |
| 30 | PA9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_TX and LCD_COM1. |
| 31 | PA10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_RX and LCD_COM2. |
| 32 | PA11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_CTS, SPI1_MISO and USB_DM. |
| 33 | PA12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_RTS, SPI1_MOSI and USB_DP. |
| 34 | PA13 | bidirectional | 5 V tolerant (FT) I/O whose main function after reset is JTMS-SWDIO (serial wire debug data). |
| 35 | VSS_2 | power_in | Ground pin of the digital supply domain. |
| 36 | VDD_2 | power_in | Digital power supply pin of the device. |
| 37 | PA14 | bidirectional | 5 V tolerant (FT) I/O whose main function after reset is JTCK-SWCLK (serial wire debug clock). |
| 38 | PA15 | bidirectional | 5 V tolerant (FT) I/O with alternate functions JTDI, TIM2_CH1_ETR, SPI1_NSS and LCD_SEG17. |
| 39 | PB3 | bidirectional | 5 V tolerant (FT) I/O with alternate functions JTDO, TIM2_CH2, SPI1_SCK, LCD_SEG7 and COMP2_INM. |
| 40 | PB4 | bidirectional | 5 V tolerant (FT) I/O with alternate functions NJTRST, TIM3_CH1, SPI1_MISO, LCD_SEG8 and COMP2_INP. |
| 41 | PB5 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SMBA, TIM3_CH2, SPI1_MOSI, LCD_SEG9 and COMP2_INP. |
| 42 | PB6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX. |
| 43 | PB7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SDA, TIM4_CH2, USART1_RX and PVD_IN. |
| 44 | BOOT0 | input | Dedicated BOOT0 pin (input-only, boot-mode selection). |
| 45 | PB8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM4_CH3, I2C1_SCL, LCD_SEG16 and TIM10_CH1. |
| 46 | PB9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM4_CH4, I2C1_SDA, LCD_COM3 and TIM11_CH1. |
| 47 | VSS_3 | power_in | Ground pin of the digital supply domain. |
| 48 | VDD_3 | power_in | Digital power supply pin of the device. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32L151C8U6A - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32l151c8u6a-etched.step/stm32l151c8u6a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l151c8u6a.step/stm32l151c8u6a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (130 pp, sha256
e5e0ab791f4e7879, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).