component
uc2843adtr
Public Unreviewedby Ray
Texas Instruments AC-DC Controllers and Regulators, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownUC2843ADTR
Texas Instruments · AC-DC Controllers and Regulators · SOIC-14
UC2843ADTR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Output of the low-impedance 1 MHz internal error amplifier and input to the peak-current-limit / PWM comparator. Open-loop gain (AVOL) is 80 dB. Maximum sink current is 6 mA and this pin is not internally current-limited. |
| 2 | FB | input | Inverting input of the error amplifier; used to close the voltage-feedback loop of the power converter for stability. Typically driven through a divider from the regulated output. |
| 3 | ISENSE | input | Input to the peak-current-limit / PWM comparator. When used with a current-sense resistor, the error amplifier output controls the pulse-by-pulse peak current in the power stage. The internal clamp limits the peak sense signal to 1 V. |
| 4 | RT/CT | input | Oscillator timing pin. Programmed with an external timing resistor RT (5 kΩ to 100 kΩ recommended) tied to VREF and a timing capacitor CT (470 pF to 4.7 nF recommended) tied to GND. Sets the oscillator frequency (up to 500 kHz). |
| 5 | GND | power_in | Controller signal ground. Serves as both the reference for all analog signals and the return for the gate-driver output on this 8-pin package (no separate PGND pin). |
| 6 | OUTPUT | output | 1 A totem-pole gate-driver output. Sources or sinks up to 1 A of gate-drive current; a series gate-driver resistor must be used to limit peak current. During UVLO the stage sinks at least 10 mA at less than 1.2 V (with VCC above 5 V). |
| 7 | VCC | power_in | Bias input for the controller and the gate driver (30 V absolute max, 11 V recommended minimum operating). Requires a local bypass capacitor at least 10× the gate capacitance of the driven main switching FET. UVLO thresholds for the '3A' variant are 8.4 V ON / 7.6 V OFF. |
| 8 | VREF | power_out | Trimmed 5 V bandgap reference output (5.00 V ±1% for UC184xA/UC284xA, ±2% for UC384xA). Must supply no more than 10 mA externally and is short-circuit protected at roughly 100 mA. Requires a 1 µF high-frequency bypass capacitor; VCC bypass must be at least 10× the VREF capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
UC2843ADTRUC2843ADTRDUC2843ADTRNUC2843ADTRPUC2843ADTRJGUC2843ADTRDWUC2843ADTRFNUC2843ADTRFK
CAD (KiCad official)
- Symbol:
UC2843ADTR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
0eebf00e4b265207, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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