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Contents

README

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CD74ACT174M96

Texas Instruments · Flip Flops · SOIC-16

CD74ACT174M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low asynchronous clear input forcing all Q outputs low; minimum pulse width 4 ns (−55°C to 125°C) or 3.5 ns (−40°C to 85°C).
2 1Q output Q output of flip-flop 1; drives up to ±24 mA with output voltage range 0.1 to 4.4 V.
3 1D input D input of flip-flop 1 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V.
4 2D input D input of flip-flop 2 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V.
5 2Q output Q output of flip-flop 2; drives up to ±24 mA with output voltage range 0.1 to 4.4 V.
6 3D input D input of flip-flop 3 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V.
7 3Q output Q output of flip-flop 3; drives up to ±24 mA with output voltage range 0.1 to 4.4 V.
8 GND power_in Ground reference pin; 0 V.
9 CLK input Positive-edge-triggered clock input; minimum pulse width 6.2 ns (−55°C to 125°C) or 5.4 ns (−40°C to 85°C); maximum frequency 80 MHz (−55°C to 125°C) or 91 MHz (−40°C to 85°C).
10 4Q output Q output of flip-flop 4; drives up to ±24 mA with output voltage range 0.1 to 4.4 V.
11 4D input D input of flip-flop 4 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V.
12 5Q output Q output of flip-flop 5; drives up to ±24 mA with output voltage range 0.1 to 4.4 V.
13 5D input D input of flip-flop 5 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V.
14 6D input D input of flip-flop 6 sampled on rising CLK edge; setup time 2 ns, hold time 2.5 ns (−55°C to 125°C) or 2.2 ns (−40°C to 85°C); requires VIH ≥ 2 V or VIL ≤ 0.8 V.
15 6Q output Q output of flip-flop 6; drives up to ±24 mA with output voltage range 0.1 to 4.4 V.
16 VCC power_in Power supply input; nominal 5 V, operating range 4.5 to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74ACT174M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74act174m96-etched.step / cd74act174m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74act174m96.step / cd74act174m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 104a411f36c5aecd, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF