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Contents

README

markdown

D1213A-02SOL-7

Diodes Incorporated · TVS · SOT-23

D1213A-02SOL-7 from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

Pinout

Pin Name Type Function
1 CH1 passive ESD-protected channel 1 input, TVS clamp to GND with 0.85 pF typical (1.2 pF max) capacitance, VRWM 3.3 V, for high-speed ports such as USB 2.0 and HDMI.
2 CH2 passive ESD-protected channel 2 input, TVS clamp to GND with 0.85 pF typical (1.2 pF max) capacitance, VRWM 3.3 V, protected to IEC 61000-4-2 ±8 kV contact and ±15 kV air.
3 GND power_in Common ground reference for both TVS channels, shown on the opposite side of the package from CH1 and CH2 in the device schematic.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Circuit Protection
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Peak Pulse Current IPP 5 A 8/20 μs, Per Fig. 2 2
ESD Protection, Contact Discharge VESD_Contact -8 8 kV Standard IEC 61000-4-2 2
ESD Protection, Air Discharge VESD_Air -15 15 kV Standard IEC 61000-4-2 2
Reverse working voltage VRWM 3.3 V 2
Reverse current IR 0.1 1 μA VR = VRWM = 3.3V 2
Reverse breakdown voltage VBR 6 7.5 9 V IR = 1mA 2
Forward voltage VF 0.6 0.8 0.95 V IF = 8mA 2
Capacitance CT 0.85 1.2 pF VR = 1.65V, f = 1MHz 2
Package Power Dissipation PD 300 mW 2
Thermal Resistance, Junction to Ambient RθJA 417 °C/W 2
Operating Temperature Range TJ -55 125 °C 2
Storage Temperature Range TSTG -65 150 °C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Matte Tin Finish annealed over Alloy 42 leadframe (Lead Free Plating). Solderable per MIL-STD-202, Method 208 1

CAD (land: KiCad; 3D: generated from the datasheet)

  • Symbol: D1213A-02SOL-7
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23, generated on the KiCad land (body 1.3 x 2.9 mm, terminals on the pads, 1.0 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: d1213a-02sol-7-etched.step / d1213a-02sol-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); d1213a-02sol-7.step / d1213a-02sol-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (4 pp, sha256 5904fec298967952, retrieved 2026-11-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

Datasheet PDF