component
SY8883DFC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, WDFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSY8883DFC
Silergy Corp · DC-DC Converters · WDFN-8-EP(2x2)
SY8883DFC from Silergy Corp, in a WDFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Output feedback pin connected to the center point of the output resistor divider to program VOUT=0.6×(1+RH/RL). |
| 2 | PG | output | Open-drain power good indicator that is low if the output is <90% or >120% of the regulation voltage and high otherwise, with a pull-up resistor to the input. |
| 3 | IN | power_in | Input supply pin (2.5V to 5.5V) to be decoupled to GND with at least a 10µF ceramic capacitor. |
| 4 | PGND | power_in | Power ground pin, shared with the exposed paddle. |
| 5 | NC | unconnected | No connection. |
| 6 | LX | power_out | Inductor pin connected to the switching node of the inductor. |
| 7 | EN | input | Enable control pin that is pulled high to turn on (VEN,H 1.2V min, VEN,L 0.4V max) and must not be floated. |
| 8 | SGND | power_in | Analog ground pin. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | WDFN-8-EP(2x2) |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | 5.5 | V | VIN = 5V, VOUT = 1.8V, L = 1.0µH, COUT = 22µF, TA = 25°C | 4 | |
| Input UVLO Threshold | VUVLO | 2.45 | 2.5 | V | 4 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | µA | VEN=0V | 4 | |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | IOUT=0.5A, CCM | 4 |
| EN Input Voltage High | VEN,H | 1.2 | V | 4 | |||
| EN Input Voltage Low | VEN,L | 0.4 | V | 4 | |||
| Input UVLO Hysteresis | VYST | 150 | mV | 4 | |||
| Quiescent Current | IQ | 55 | µA | VFB=105%×VREF | 4 | ||
| LX Node Discharge Resistance | RDIS | 50 | Ω | 4 | |||
| Top FET RON | RDS(ON)1 | 85 | mΩ | 4 | |||
| Bottom FET RON | RDS(ON)2 | 60 | mΩ | 4 | |||
| Switching Frequency | fSW | 1 | MHz | IOUT=0.5A, CCM | 4 | ||
| Top FET Current Limit | ILMT,TOP | 3.7 | A | 4 | |||
| Soft-start Time | tSS | 1 | ms | VOUT from 0% to 100% | 4 | ||
| Thermal Shutdown Temperature | TSD | 160 | °C | 4 | |||
| Supply Input Voltage (abs max) | -0.3 | 6 | V | 3 | |||
| FB, EN, PG Voltage (abs max) | -0.3 | V | max is VIN + 0.6V | 3 | |||
| LX Voltage (abs max) | -0.3 | 6 | V | Tested down to -3V <20ns; up to +7V <20ns | 3 | ||
| Power Dissipation | PD | 1.4 | W | TA = 25°C | 3 | ||
| Junction Temperature Range (abs max) | -40 | 150 | °C | 3 | |||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Supply Input Voltage (recommended) | 2.5 | 5.5 | V | 3 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range | -40 | 85 | °C | 3 | |||
| Thermal Resistance Junction-Ambient | θJA | 70 | °C/W | Natural convection, TA = 25°C, 2-oz two-layer Silergy evaluation board | 3 | ||
| Thermal Resistance Junction-Case | θJC | 25 | °C/W | Paddle is case position | 3 |
CAD (KiCad official)
- Symbol:
SY8883DFC - Footprint:
Package_DFN_QFN:WDFN-8-1EP_2x2mm_P0.5mm_EP0.8x1.2mm - 3D model: WDFN-8-EP(2x2), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sy8883dfc-etched.step/sy8883dfc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8883dfc.step/sy8883dfc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (11 pp, sha256
b59c153f007c0b4c, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).