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TLV274IN

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Texas Instruments Operational Amplifier, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifierstlv274infactory-2.0.0extractor-text

Verified TLV274IN

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TLV274IN · PDIP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 50-page datasheet
  • ✓distributor: lcsc C1347999, digikey 2156-TLV274IN-ND, mouser 595-TLV274IN
  • ✓family: DIP-14_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-97677082/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tlv274in.kicad_sym✓ tlv274in.kicad_mod✓ tlv274in.step
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Symbol & Footprint

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Contents

README

markdown

TLV274IN

Texas Instruments · Operational Amplifier · PDIP-14

TLV274IN from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of channel 1 (the TLV27x family is specified with rail-to-rail output).
2 1IN- input Inverting input of channel 1; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
3 1IN+ input Noninverting input of channel 1; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
4 VDD power_in Positive supply; single-supply operation is 2.7 V to 16 V and split-supply operation is ±1.35 V to ±8 V.
5 2IN+ input Noninverting input of channel 2; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
6 2IN- input Inverting input of channel 2; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
7 2OUT output Output of channel 2 (the TLV27x family is specified with rail-to-rail output).
8 3OUT output Output of channel 3 (the TLV27x family is specified with rail-to-rail output).
9 3IN- input Inverting input of channel 3; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
10 3IN+ input Noninverting input of channel 3; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
11 GND power_in Negative supply or ground for single-supply operation.
12 4IN+ input Noninverting input of channel 4; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
13 4IN- input Inverting input of channel 4; the common-mode input voltage range is 0 V to VDD − 1.35 V per the recommended operating conditions.
14 4OUT output Output of channel 4 (the TLV27x family is specified with rail-to-rail output).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Amplifiers
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VDD VDD 16.5 V 6
Input current, II II -10 10 mA 6
Output current, IO IO -100 100 mA 6
Operating free-air temperature, TA TA -40 125 °C I-suffix 6
Junction temperature, TJ TJ 150 °C 6
Storage temperature, Tstg Tstg -65 150 °C 6
Supply voltage, VDD (single-supply) VDD 2.7 16 V Single-supply 6
Supply voltage, VDD (split-supply) VDD 1.35 8 V Split-supply; printed as ±1.35 V to ±8 V 6
Common-mode input voltage, VICR VICR 0 V Printed maximum is VDD − 1.35 V (expression, not numeric) 6
Operating free-air temperature, TA TA -40 125 °C I-suffix 6
Input offset voltage, VIO VIO 0.5 5 mV 25°C; VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω 8
Input offset voltage, VIO VIO 7 mV Full range; VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω 8
Common-mode rejection ratio, CMRR CMRR 58 70 dB 25°C; VDD = 2.7 V; VIC = 0 to VDD − 1.35 V; RS = 50 Ω 8
Common-mode rejection ratio, CMRR CMRR 55 dB Full range; VDD = 2.7 V; VIC = 0 to VDD − 1.35 V; RS = 50 Ω 8
Common-mode rejection ratio, CMRR CMRR 65 80 dB 25°C; VDD = 5 V; VIC = 0 to VDD − 1.35 V; RS = 50 Ω 8
Common-mode rejection ratio, CMRR CMRR 62 dB Full range; VDD = 5 V; VIC = 0 to VDD − 1.35 V; RS = 50 Ω 8
Common-mode rejection ratio, CMRR CMRR 69 85 dB 25°C; VDD = ±5 V; VIC = −5 V to VDD − 1.35 V; RS = 50 Ω 8
Common-mode rejection ratio, CMRR CMRR 66 dB Full range; VDD = ±5 V; VIC = −5 V to VDD − 1.35 V; RS = 50 Ω 8
Large-signal differential voltage amplification, AVD AVD 97 106 dB 25°C; VDD = 2.7 V; VO(PP) = VDD/2; RL = 10 kΩ 8
Large-signal differential voltage amplification, AVD AVD 76 dB Full range; VDD = 2.7 V; VO(PP) = VDD/2; RL = 10 kΩ 8
Large-signal differential voltage amplification, AVD AVD 100 110 dB 25°C; VDD = 5 V; VO(PP) = VDD/2; RL = 10 kΩ 8
Large-signal differential voltage amplification, AVD AVD 86 dB Full range; VDD = 5 V; VO(PP) = VDD/2; RL = 10 kΩ 8
Large-signal differential voltage amplification, AVD AVD 100 115 dB 25°C; VDD = ±5 V; VO(PP) = VDD/2; RL = 10 kΩ 8
Large-signal differential voltage amplification, AVD AVD 90 dB Full range; VDD = ±5 V; VO(PP) = VDD/2; RL = 10 kΩ 8
Input offset current, IIO IIO 1 60 pA 25°C; VDD = 5 V; VIC = VDD/2; VO = VDD/2; RS = 50 Ω 8
Input offset current, IIO IIO 1000 pA 125°C; VDD = 5 V; VIC = VDD/2; VO = VDD/2; RS = 50 Ω 8
Input bias current, IIB IIB 1 60 pA 25°C; VDD = 5 V; VIC = VDD/2; VO = VDD/2; RS = 50 Ω 8
Input bias current, IIB IIB 1000 pA 125°C; VDD = 5 V; VIC = VDD/2; VO = VDD/2; RS = 50 Ω 8
High-level output voltage, VOH VOH 2.55 2.58 V 25°C; VIC = VDD/2; IOH = −1 mA; VDD = 2.7 V 9
High-level output voltage, VOH VOH 2.48 V Full range; VIC = VDD/2; IOH = −1 mA; VDD = 2.7 V 9
High-level output voltage, VOH VOH 4.9 4.93 V 25°C; VIC = VDD/2; IOH = −1 mA; VDD = 5 V 9
High-level output voltage, VOH VOH 4.85 V Full range; VIC = VDD/2; IOH = −1 mA; VDD = 5 V 9
High-level output voltage, VOH VOH 4.92 4.96 V 25°C; VIC = VDD/2; IOH = −1 mA; VDD = ±5 V 9
High-level output voltage, VOH VOH 4.9 V Full range; VIC = VDD/2; IOH = −1 mA; VDD = ±5 V 9
Low-level output voltage, VOL VOL 0.1 0.15 V 25°C; VIC = VDD/2; IOH = 1 mA (as printed); VDD = 2.7 V 9
Low-level output voltage, VOL VOL 0.22 V Full range; VIC = VDD/2; IOH = 1 mA (as printed); VDD = 2.7 V 9
Low-level output voltage, VOL VOL 0.05 0.1 V 25°C; VIC = VDD/2; IOH = 1 mA (as printed); VDD = 5 V 9
Low-level output voltage, VOL VOL 0.15 V Full range; VIC = VDD/2; IOH = 1 mA (as printed); VDD = 5 V 9
Low-level output voltage, VOL VOL -4.95 -4.92 V 25°C; VIC = VDD/2; IOH = 1 mA (as printed); VDD = ±5 V 9
Low-level output voltage, VOL VOL -4.9 V Full range; VIC = VDD/2; IOH = 1 mA (as printed); VDD = ±5 V 9
Supply current per channel, IDD IDD 470 560 µA 25°C; VO = VDD/2; VDD = 2.7 V 10
Supply current per channel, IDD IDD 550 660 µA 25°C; VO = VDD/2; VDD = 5 V 10
Supply current per channel, IDD IDD 625 800 µA 25°C; VO = VDD/2; VDD = 10 V 10
Supply current per channel, IDD IDD 1000 µA Full range; VO = VDD/2; VDD = 10 V 10
Supply voltage rejection ratio, PSRR PSRR 70 80 dB 25°C; VDD = 2.7 V to 16 V; VIC = VDD/2; no load 10
Supply voltage rejection ratio, PSRR PSRR 65 dB Full range; VDD = 2.7 V to 16 V; VIC = VDD/2; no load 10
Slew rate at unity gain, SR SR 1.35 2.1 V/µs 25°C; VO(PP) = VDD/2; CL = 50 pF; RL = 10 kΩ; VDD = 2.7 V 10
Slew rate at unity gain, SR SR 1 V/µs Full range; VO(PP) = VDD/2; CL = 50 pF; RL = 10 kΩ; VDD = 2.7 V 10
Slew rate at unity gain, SR SR 1.45 2.4 V/µs 25°C; VO(PP) = VDD/2; CL = 50 pF; RL = 10 kΩ; VDD = 5 V 10
Slew rate at unity gain, SR SR 1.2 V/µs Full range; VO(PP) = VDD/2; CL = 50 pF; RL = 10 kΩ; VDD = 5 V 10
Slew rate at unity gain, SR SR 1.8 2.6 V/µs 25°C; VO(PP) = VDD/2; CL = 50 pF; RL = 10 kΩ; VDD = ±5 V 10
Slew rate at unity gain, SR SR 1.3 V/µs Full range; VO(PP) = VDD/2; CL = 50 pF; RL = 10 kΩ; VDD = ±5 V 10
Junction-to-ambient thermal resistance, RθJA RθJA 66.3 °C/W PDIP-14 (N) package 7
Junction-to-case (top) thermal resistance, RθJC(top) RθJC(top) 20.5 °C/W PDIP-14 (N) package 7
Junction-to-board thermal resistance, RθJB RθJB 26.8 °C/W PDIP-14 (N) package 7
Junction-to-top characterization parameter, ψJT ψJT 2.1 °C/W PDIP-14 (N) package 7
Junction-to-board characterization parameter, ψJB ψJB 26.2 °C/W PDIP-14 (N) package 7

CAD (KiCad official)

  • Symbol: TLV274IN
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: tlv274in-etched.step / tlv274in-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv274in.step / tlv274in.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 08d1cc5a8cc926f3, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF