component
74HCT367D
Public Made by Adomby adom
Nexperia Logic ICs, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HCT367D
Nexperia · Logic ICs · SO-16
74HCT367D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable input (active LOW); a HIGH on nOE causes the outputs to assume a high-impedance OFF-state. |
| 2 | 1A | input | Data input 1A; inputs include clamp diodes, so current-limiting resistors can be used to interface the input to voltages above VCC. |
| 3 | 1Y | tri_state | 3-state bus output 1Y, which is high-impedance (Z) when the output enable nOE is HIGH. |
| 4 | 2A | input | Data input 2A; inputs include clamp diodes, so current-limiting resistors can be used to interface the input to voltages above VCC. |
| 5 | 2Y | tri_state | 3-state bus output 2Y, which is high-impedance (Z) when the output enable nOE is HIGH. |
| 6 | 3A | input | Data input 3A; inputs include clamp diodes, so current-limiting resistors can be used to interface the input to voltages above VCC. |
| 7 | 3Y | tri_state | 3-state bus output 3Y, which is high-impedance (Z) when the output enable nOE is HIGH. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | 4Y | tri_state | 3-state bus output 4Y, which is high-impedance (Z) when the output enable nOE is HIGH. |
| 10 | 4A | input | Data input 4A; inputs include clamp diodes, so current-limiting resistors can be used to interface the input to voltages above VCC. |
| 11 | 5Y | tri_state | 3-state bus output 5Y, which is high-impedance (Z) when the output enable nOE is HIGH. |
| 12 | 5A | input | Data input 5A; inputs include clamp diodes, so current-limiting resistors can be used to interface the input to voltages above VCC. |
| 13 | 6Y | tri_state | 3-state bus output 6Y, which is high-impedance (Z) when the output enable nOE is HIGH. |
| 14 | 6A | input | Data input 6A; inputs include clamp diodes, so current-limiting resistors can be used to interface the input to voltages above VCC. |
| 15 | 2OE | input | Output enable input (active LOW); a HIGH on nOE causes the outputs to assume a high-impedance OFF-state. |
| 16 | VCC | power_in | Supply voltage; the recommended range for 74HCT367 is 4.5 V to 5.5 V, with an absolute maximum of +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -35 | 35 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| supply current | ICC | 70 | mA | 4 | |||
| ground current | IGND | -70 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | [1] For SOT109-1 (SO16): derates linearly with 12.4 mW/K above 110 °C | 4 | ||
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| input voltage | VI | 0 | V | 4 | |||
| output voltage | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 6 | ||
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | IO = -20 μA; VI = VIH or VIL; VCC = 4.5 V; 25 °C | 6 | |
| HIGH-level output voltage | VOH | 4.4 | V | IO = -20 μA; VI = VIH or VIL; VCC = 4.5 V; -40 °C to +85 °C | 6 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | IO = -6 mA; VI = VIH or VIL; VCC = 4.5 V; 25 °C | 6 | |
| HIGH-level output voltage | VOH | 3.84 | V | IO = -6 mA; VI = VIH or VIL; VCC = 4.5 V; -40 °C to +85 °C | 6 | ||
| HIGH-level output voltage | VOH | 3.7 | V | IO = -6 mA; VI = VIH or VIL; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | IO = 20 μA; VI = VIH or VIL; VCC = 4.5 V; 25 °C | 6 | |
| LOW-level output voltage | VOL | 0.1 | V | IO = 20 μA; VI = VIH or VIL; VCC = 4.5 V; -40 °C to +85 °C | 6 | ||
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | IO = 6.0 mA; VI = VIH or VIL; VCC = 4.5 V; 25 °C | 6 | |
| LOW-level output voltage | VOL | 0.33 | V | IO = 6.0 mA; VI = VIH or VIL; VCC = 4.5 V; -40 °C to +85 °C | 6 | ||
| LOW-level output voltage | VOL | 0.4 | V | IO = 6.0 mA; VI = VIH or VIL; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; 25 °C | 6 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C | 6 | |
| OFF-state output current | IOZ | -0.5 | 0.5 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; 25 °C | 6 | |
| OFF-state output current | IOZ | -5 | 5 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +85 °C | 6 | |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +125 °C | 6 | |
| supply current | ICC | 8 | μA | VI = VCC or GND; VCC = 5.5 V; IO = 0 A; 25 °C | 6 | ||
| supply current | ICC | 80 | μA | VI = VCC or GND; VCC = 5.5 V; IO = 0 A; -40 °C to +85 °C | 6 | ||
| supply current | ICC | 160 | μA | VI = VCC or GND; VCC = 5.5 V; IO = 0 A; -40 °C to +125 °C | 6 | ||
| additional supply current, 1OE and nA inputs | ΔICC | 100 | 360 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; 25 °C | 6 | |
| additional supply current, 1OE and nA inputs | ΔICC | 450 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +85 °C | 6 | ||
| additional supply current, 1OE and nA inputs | ΔICC | 490 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +125 °C | 6 | ||
| additional supply current, 2OE input | ΔICC | 90 | 324 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; 25 °C | 6 | |
| additional supply current, 2OE input | ΔICC | 405 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +85 °C | 6 | ||
| additional supply current, 2OE input | ΔICC | 441 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +125 °C | 6 | ||
| propagation delay nA to nY | tpd | 14 | 25 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; 25 °C | 7 | |
| propagation delay nA to nY | tpd | 31 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; -40 °C to +85 °C | 7 | ||
| propagation delay nA to nY | tpd | 38 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| enable time nOE to nY | ten | 16 | 35 | ns | nOE to nY; see Fig. 7; VCC = 4.5 V; 25 °C | 7 | |
| enable time nOE to nY | ten | 44 | ns | nOE to nY; see Fig. 7; VCC = 4.5 V; -40 °C to +85 °C | 7 | ||
| enable time nOE to nY | ten | 53 | ns | nOE to nY; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| disable time nOE to nY | tdis | 21 | 35 | ns | nOE to nY; see Fig. 7; VCC = 4.5 V; 25 °C | 7 | |
| disable time nOE to nY | tdis | 44 | ns | nOE to nY; see Fig. 7; VCC = 4.5 V; -40 °C to +85 °C | 7 | ||
| disable time nOE to nY | tdis | 53 | ns | nOE to nY; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| transition time | tt | 5 | 12 | ns | see Fig. 6; VCC = 4.5 V; 25 °C | 7 | |
| transition time | tt | 15 | ns | see Fig. 6; VCC = 4.5 V; -40 °C to +85 °C | 7 | ||
| transition time | tt | 18 | ns | see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 7 |
CAD (KiCad official)
- Symbol:
74HCT367D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
74hct367d-etched.step/74hct367d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct367d.step/74hct367d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
10ef4d7fe093b3f7, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).