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DSC1001CL2-100.0000T

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Microchip Tech Pre-ordered MCUs, SMD3225-4P. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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DSC1001CL2-100.0000T

Microchip Tech · Pre-ordered MCUs · SMD3225-4P

DSC1001CL2-100.0000T from Microchip Tech, in a SMD3225-4P. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 STANDBY# input Standby input: high level or open (no connect) enables the output, low level puts the output (pin 3) in high impedance, with VIH min 0.75 x VDD and VIL max 0.25 x VDD.
2 GND power_in Power supply ground.
3 OUT output Oscillator CMOS output, high impedance when STANDBY# is low, recommended load R > 10 kΩ and C ≤ 15 pF (DSC1001).
4 VDD power_in Positive power supply, recommended operating range +1.7V to +3.6V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SMD3225-4P
Category Embedded Processors & Controllers
Pins 4

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Frequency Tolerance ∆f -25 25 ppm Includes initial tolerance, temperature and power supply voltage 3
Frequency F0 1 150 MHz Single Frequency 3
Aging ∆f -5 5 ppm 1 year @ +25°C 3
Supply Current, Standby IDD 15 µA T = +25°C 3
Output Startup Time tSU 1 1.3 ms T = +25°C 3
Output Disable Time tDA 20 100 ns 3
Output Duty Cycle SYM 45 55 % 3
Input Logic Level High VIH 0.75 x VDD 3
Input Logic Level Low VIL 0.25 x VDD 3
Supply Current, No Load IDD 6 6.3 mA VDD = 1.8V, 1 MHz, CL = 0 pF, RL = ∞, T = +25°C 3
Supply Current, No Load IDD 6.5 7.1 mA VDD = 1.8V, 27 MHz, CL = 0 pF, RL = ∞, T = +25°C 3
Supply Current, No Load IDD 7.2 8.5 mA VDD = 1.8V, 70 MHz, CL = 0 pF, RL = ∞, T = +25°C 3
Supply Current, No Load IDD 8.3 11.9 mA VDD = 1.8V, 150 MHz, CL = 0 pF, RL = ∞, T = +25°C 3
Output Logic Level High VOH 0.8 x VDD VDD = 1.8V, -4 mA, DSC1001, CL = 15 pF 3
Output Logic Level Low VOL 0.2 x VDD VDD = 1.8V, 4 mA, DSC1001, CL = 15 pF 3
Output Transition Rise Time tR 1.4 3 ns VDD = 1.8V, DSC1001, CL = 15 pF, T = +25°C, 20% to 80% 4
Output Transition Fall Time tF 1 3 ns VDD = 1.8V, DSC1001, CL = 15 pF, T = +25°C, 20% to 80% 4
Jitter, Max. Cycle-to-Cycle JCC 60 ps VDD = 1.8V, f = 100 MHz (Note 2) 4
Period Jitter JP 10 15 psRMS VDD = 1.8V, f = 100 MHz (Note 2) 4
Supply Current, No Load IDD 6 6.4 mA VDD = 2.5V, 1 MHz, CL = 0 pF, RL = ∞, T = +25°C 4
Supply Current, No Load IDD 6.7 7.5 mA VDD = 2.5V, 27 MHz, CL = 0 pF, RL = ∞, T = +25°C 4
Supply Current, No Load IDD 7.7 9.4 mA VDD = 2.5V, 70 MHz, CL = 0 pF, RL = ∞, T = +25°C 4
Supply Current, No Load IDD 9.6 13.9 mA VDD = 2.5V, 150 MHz, CL = 0 pF, RL = ∞, T = +25°C 4
Output Logic Level High VOH 0.8 x VDD VDD = 2.5V, -4 mA, DSC1001, CL = 15 pF 4
Output Logic Level Low VOL 0.2 x VDD VDD = 2.5V, 4 mA, DSC1001, CL = 15 pF 4
Output Transition Rise Time tR 1 2 ns VDD = 2.5V, DSC1001, CL = 15 pF, T = +25°C, 20% to 80% 4
Output Transition Fall Time tF 0.9 2 ns VDD = 2.5V, DSC1001, CL = 15 pF, T = +25°C, 20% to 80% 4
Jitter, Max. Cycle-to-Cycle JCC 50 ps VDD = 2.5V, f = 100 MHz (Note 2) 5
Period Jitter JP 5 10 psRMS VDD = 2.5V, f = 100 MHz (Note 2) 5
Supply Current, No Load IDD 6 6.5 mA VDD = 3.3V, 1 MHz, CL = 0 pF, RL = ∞, T = +25°C 5
Supply Current, No Load IDD 6.8 8 mA VDD = 3.3V, 27 MHz, CL = 0 pF, RL = ∞, T = +25°C 5
Supply Current, No Load IDD 8.2 10.5 mA VDD = 3.3V, 70 MHz, CL = 0 pF, RL = ∞, T = +25°C 5
Supply Current, No Load IDD 10.8 16.6 mA VDD = 3.3V, 150 MHz, CL = 0 pF, RL = ∞, T = +25°C 5
Output Logic Level High VOH 0.8 x VDD VDD = 3.3V, -4 mA, DSC1001, CL = 15 pF 5
Output Logic Level Low VOL 0.2 x VDD VDD = 3.3V, 4 mA, DSC1001, CL = 15 pF 5
Output Transition Rise Time tR 1 2 ns VDD = 3.3V, DSC1001, CL = 15 pF, T = +25°C, 20% to 80% 5
Output Transition Fall Time tF 0.9 2 ns VDD = 3.3V, DSC1001, CL = 15 pF, T = +25°C, 20% to 80% 5
Input Voltage VIN -0.3 V Lower limit; upper limit is VDD + 0.3V 3
Supply Voltage VDD 1.7 3.6 V 3
Output Load Resistance ZL 10 kΩ R > 10 kΩ 3
Output Load Capacitance ZL 15 pF C ≤ 15 pF 3
Operating Temperature Range TA -40 105 °C Ordering Option L 6
Junction Operating Temperature TJ 150 °C 6
Storage Temperature Range TA -55 150 °C 6
Soldering Temperature Range TS 260 °C 40 sec. max 6

CAD (KiCad official)

  • Symbol: DSC1001CL2-100.0000T
  • Footprint: Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm
  • 3D model: SMD3225-4P (KiCad packages3D, STEP)
  • 3D model files: dsc1001cl2-100-0000t-etched.step / dsc1001cl2-100-0000t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dsc1001cl2-100-0000t.step / dsc1001cl2-100-0000t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (24 pp, sha256 6cde4a9ee2c6621b, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF