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Contents

README

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SN65HVD62RGTR

Texas Instruments · RS-485 / RS-422 ICs · QFN-16-EP(3x3)

SN65HVD62RGTR from Texas Instruments, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNCOUT tri_state Open drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1,2 (8.704 MHz for HVD62).
2 TXIN input Digital data bit stream to driver.
3 VL power_in Logic supply voltage for the device, operating range 1.6V to 5.5V.
4 RXOUT output Digital data bit stream from receiver.
5 DIR output Direction control output signal for bus arbitration.
6 DIRSET2 input Control bit 2 to set duration of DIR; DIRSET[2,1]: [L,L]=9.6kbps, [L,H]=38.4kbps, [H,L]=115kbps, [H,H]=Standby Mode.
7 DIRSET1 input Control bit 1 to set duration of DIR; DIRSET[2,1]: [L,L]=9.6kbps, [L,H]=38.4kbps, [H,L]=115kbps, [H,H]=Standby Mode.
8 GND power_in Ground, reference potential.
9 RES input Input voltage to adjust driver output power set by external resistors from BIAS pin to GND, voltage range 0.7V to 1.5V.
10 BIAS output Bias voltage output for setting driver output power by external resistors.
11 RXIN input Modulated input signal to the receiver with input signal amplitude of 1.12 Vpp at 2.176 MHz.
12 TXOUT output Modulated output signal from the driver at center frequency 2.176 MHz.
13 VCC power_in Analog supply voltage for the device, operating range 3V to 5.5V.
14 XTAL1 input Crystal oscillator I/O pin; connect a 4x frequency crystal between this pin and XTAL2, or connect to 8.704 MHz clock input.
15 XTAL2 input Crystal oscillator I/O pin; connect a 4x frequency crystal between XTAL1 and this pin, or connect to GND for clock input mode.
16 GND power_in Ground, reference potential.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-16-EP(3x3)
Category Interface
Pins 17

CAD (KiCad official)

  • Symbol: SN65HVD62RGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: sn65hvd62rgtr-etched.step / sn65hvd62rgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd62rgtr.step / sn65hvd62rgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 fa1a4050145cc5e6, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF