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A4988SETTR-T

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Allegro MicroSystems LLC Stepper Motor Driver, WQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsa4988settr-tfactory-2.0.0extractor-text
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Contents

README

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A4988SETTR-T

Allegro MicroSystems LLC · Stepper Motor Driver · WQFN-28-EP(5x5)

A4988SETTR-T from Allegro MicroSystems LLC, in a WQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT2B output DMOS Full Bridge 2 Output B.
2 ENABLE input Logic input: when set high all FET outputs are disabled, and when set low the internal control enables the outputs as required; STEP, DIR and MSx remain active regardless of its state.
3 GND power_in Ground; internally fused for thermal dissipation and must be tied together externally to the PAD ground plane under the device.
4 CP1 passive Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
5 CP2 passive Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
6 VCP passive Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBB, and an undervoltage on VCP disables the FET outputs.
7 NC unconnected No connection.
8 VREG passive Regulator decoupling terminal; nominal output 7 V, to be decoupled with a 0.22 µF ceramic capacitor to ground.
9 MS1 input Logic input for microstep select; MS1 has a 100 kΩ pull-down resistance.
10 MS2 input Logic input for microstep select; MS2 has a 50 kΩ pull-down resistance.
11 MS3 input Logic input for microstep select; MS3 has a 100 kΩ pull-down resistance.
12 RESET input Logic input that sets the translator to the predefined Home state and turns off all FET outputs; STEP inputs are ignored while RESET is low.
13 ROSC passive Timing set terminal: tied to VDD or to ground gives a 30 µs fixed off-time, and a resistor to ground sets tOFF ≈ ROSC/825 µs (ROSC in kΩ, tOFF in µs).
14 SLEEP input Logic input; a logic low puts the device into Sleep mode, disabling the output FETs, current regulator and charge pump, and a 1 ms delay is needed before a STEP command after leaving Sleep.
15 VDD power_in Logic supply; operating range 3.0 to 5.5 V, with absolute maximum rating -0.3 to 5.5 V.
16 STEP input Logic input; each low-to-high transition advances the motor one microstep.
17 REF input Gm reference voltage input; VREF operating range is 0 to 4 V and sets the maximum current trip level via ITripMAX = VREF/(8×RS).
18 GND power_in Ground; internally fused for thermal dissipation and must be tied together externally to the PAD ground plane under the device.
19 DIR input Logic input that sets the direction of rotation; changes take effect only on the next STEP rising edge.
20 NC unconnected No connection.
21 OUT1B output DMOS Full Bridge 1 Output B.
22 VBB1 power_in Load supply for Bridge 1; operating range 8 to 35 V, with absolute maximum rating 35 V.
23 SENSE1 passive Sense resistor terminal for Bridge 1; the sense voltage must not exceed the 0.5 V maximum rating.
24 OUT1A output DMOS Full Bridge 1 Output A.
25 NC unconnected No connection.
26 OUT2A output DMOS Full Bridge 2 Output A.
27 SENSE2 passive Sense resistor terminal for Bridge 2; the sense voltage must not exceed the 0.5 V maximum rating.
28 VBB2 power_in Load supply for Bridge 2; operating range 8 to 35 V, with absolute maximum rating 35 V.
29 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems LLC
Package WQFN-28-EP(5x5)
Category Motor Driver ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage Range VBB 8 35 V Operating 4
Logic Supply Voltage Range VDD 3 5.5 V Operating 4
Output On Resistance, Source Driver RDSON 320 430 mΩ Source Driver, IOUT = -1.5 A 4
Output On Resistance, Sink Driver RDSON 320 430 mΩ Sink Driver, IOUT = 1.5 A 4
Body Diode Forward Voltage, Source Diode VF 1.2 V Source Diode, IF = -1.5 A 4
Body Diode Forward Voltage, Sink Diode VF 1.2 V Sink Diode, IF = 1.5 A 4
Motor Supply Current IBB 4 mA fPWM < 50 kHz 4
Motor Supply Current IBB 2 mA Operating, outputs disabled 4
Logic Supply Current IDD 8 mA fPWM < 50 kHz 4
Logic Supply Current IDD 5 mA Outputs off 4
Logic Input Current (high) IIN(1) -20 1 20 µA VIN = VDD×0.7 4
Logic Input Current (low) IIN(0) -20 1 20 µA VIN = VDD×0.3 4
Logic Input Hysteresis VHYS(IN) 5 11 19 % As a % of VDD 4
Blank Time tBLANK 0.7 1 1.3 μs 4
Fixed Off-Time tOFF 20 30 40 μs OSC = VDD or GND 4
Fixed Off-Time tOFF 23 30 37 μs ROSC = 25 kΩ 4
Reference Input Voltage Range VREF 0 4 V 4
Reference Input Current IREF -3 0 3 μA 4
Current Trip-Level Error errI -15 15 % VREF = 2 V, %ITripMAX = 38.27% 4
Current Trip-Level Error errI -5 5 % VREF = 2 V, %ITripMAX = 70.71% 4
Crossover Dead Time tDT 100 475 800 ns 4
Overcurrent Protection Threshold IOCPST 2.1 A 4
VDD Undervoltage Lockout VDDUVLO 2.7 2.8 2.9 V VDD rising 4
Load Supply Voltage (absolute maximum) VBB 35 V 2
Output Current IOUT -2 2 A 2
Logic Input Voltage (absolute maximum) VIN -0.3 5.5 V 2
Logic Supply Voltage (absolute maximum) VDD -0.3 5.5 V 2
Motor Outputs Voltage VOUT -2 37 V 2
Sense Voltage VSENSE -0.5 0.5 V 2
Reference Voltage (absolute maximum) VREF 5.5 V 2
Operating Ambient Temperature, Range S TA -20 85 ºC Range S 2
Maximum Junction Temperature TJ(max) 150 ºC 2
Storage Temperature Tstg -55 150 ºC 2
Package Thermal Resistance RθJA 32 ºC/W Four-layer PCB, based on JEDEC standard 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin exposed pad for enhanced thermal dissipation. It is lead (Pb) free (suffix -T), with 100% matte tin plated leadframes. 2

CAD (KiCad official)

  • Symbol: A4988SETTR-T
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: WQFN-28-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: a4988settr-t-etched.step / a4988settr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4988settr-t.step / a4988settr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems LLC datasheet (20 pp, sha256 f90ca559dbe3809e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF