DRV8805DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VM	power_in	Device power supply; connect to motor supply, 8.2 V to 60 V.
2	VCLAMP	passive	Output clamp voltage; connect to VM supply or a Zener diode to VM supply, with clamp voltage rated 0 V to 60 V.
3	OUT1	output	Output 1; connect to load 1; NMOS low-side driver rated 1.5 A single channel on or 800 mA four channels on (SOIC, 25°C).
4	OUT2	output	Output 2; connect to load 2; NMOS low-side driver rated 1.5 A single channel on or 800 mA four channels on (SOIC, 25°C).
5	GND	power_in	Device ground; all pins must be connected to GND.
6	GND	power_in	Device ground; all pins must be connected to GND.
7	GND	power_in	Device ground; all pins must be connected to GND.
8	OUT3	output	Output 3; connect to load 3; NMOS low-side driver rated 1.5 A single channel on or 800 mA four channels on (SOIC, 25°C).
9	OUT4	output	Output 4; connect to load 4; NMOS low-side driver rated 1.5 A single channel on or 800 mA four channels on (SOIC, 25°C).
10	nENBL	input	Enable input; active low enables outputs; internal pulldown.
11	RESET	input	Reset input; active-high reset initializes internal logic; internal pulldown.
12	SM1	input	Step mode input; sets step mode (see step modes section); internal pulldown.
13	SM0	input	Step mode input; sets step mode (see step modes section); internal pulldown.
14	GND	power_in	Device ground; all pins must be connected to GND.
15	GND	power_in	Device ground; all pins must be connected to GND.
16	GND	power_in	Device ground; all pins must be connected to GND.
17	DIR	input	Direction input; level controls direction of rotation; internal pulldown.
18	STEP	input	Step input; rising edge advances motor to next step; internal pulldown.
19	nHOME	output	Home output; logic low when indexer is at home position; push-pull structure.
20	nFAULT	output	Fault output; logic low when in fault condition (overtemp, overcurrent); open-drain.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-20-300mil
Category	Power Supply Chip
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VM Power supply voltage	VM	-0.3		65	V		4
VOUTx Output voltage	VOUTx	-0.3		65	V		4
VCLAMP Clamp voltage	VCLAMP	-0.3		65	V		4
Digital input pin voltage		-0.5		7	V		4
nHOME,nFAULT digital output pin voltage		-0.5		7	V		4
nHOME,nFAULT output current				20	mA		4
Peak clamp diode current				2	A		4
DC or RMS clamp diode current				1	A		4
Operating virtual junction temperature	TJ	-40		150	°C		4
Storage temperature	Tstg	-60		150	°C		4
VM Power supply voltage	VM	8.2		60	V		4
VCLAMP Output clamp voltage	VCLAMP	0		60	V		4
Continuous output current, single channel on, SOIC package	IOUT			1.5	A	TA = 25°C, SOIC package	4
Continuous output current, four channels on, SOIC package	IOUT			0.8	A	TA = 25°C, SOIC package	4
VM operating supply current	IVM		1.6	2.1	mA	VM = 24 V	5
Input low voltage	VIL		0.6	0.7	V		5
Input low current	IIL	-20		20	μA	VIN = 0	5
Output high voltage, steady state	VOH	3.3	4.5	5.6	V	IO = 100 μA, VM = 11 V, 60 V, steady state	5
FET on resistance	RDS(ON)		0.75	0.8	Ω	VM = 24 V, IO = 700 mA, TJ = 85°C	5
Off-state leakage current, low-side FETs	IOFF	-50		50	μA		5
Off-state leakage current, high-side diodes	IOFF	-50		50	μA	VM = 24 V, TJ = 25°C	5
Rise time	tR	50		300	ns	VM = 24 V, IO = 700 mA, Resistive load	5
Fall time	tF	50		300	ns	VM = 24 V, IO = 700 mA, Resistive load	5
Overcurrent protection trip level	IOCP	2.3		3.8	A		6
Thermal shutdown temperature	tTSD	150	160	180	°C	Die temperature	6
Step frequency	fSTEP			250	kHz		6
Pulse duration, STEP high	tWH(STEP)	1.9			µs		6
Pulse duration, STEP low	tWL(STEP)	1.9			µs		6
Setup time, DIR, SMx to STEP rising	tSU(STEP)	1			µs		6
Hold time, DIR, SMx to STEP rising	tH(STEP)	1			µs		6
Enable time, nENBL to output low	tOE(ENABLE)			50	ns		6
Propagation delay time, STEP to OUTx, low to high	tPD(L-H)			500	ns		6
Propagation delay time, STEP to OUTx, high to low	tPD(H-L)			500	ns		6
RESET pulse width	tRESET	20			µs		6
Input high current	IIH		100		μA	VIN = 3.3 V	5
VM undervoltage lockout voltage	VUVLO		8.2		V	VM rising	5
Input high voltage	VIH		2		V		5
Input hysteresis	VHYS		0.45		V		5
Pulldown resistance	RPD		100		kΩ		5
nFAULT output low voltage	VOL		0.5		V	IO = 5 mA	5
nFAULT output high leakage current	IOH		1		μA	VO = 3.3 V	5
nHOME output low voltage	VOL		0.5		V	IO = 5 mA	5
Output high voltage, peak	VOH		6.5		V	IO = 100 µA, VM = 11 V, 60 V, peak	5
Output high voltage, steady state	VOH		2.5		V	IO = 100 μA, VM = 8.2 V, 11 V, steady state	5
Output source current	ISRC		1		mA	VM = 24 V	5
Output sink current	ISNK		5		mA	VM = 24 V	5
FET on resistance	RDS(ON)		0.5		Ω	VM = 24 V, IO = 700 mA, TJ = 25°C	5
Diode forward voltage	VF		1.2		V	VM = 24 V, IO = 700 mA, TJ = 25°C	5
Overcurrent protection deglitch time	tOCP		3.5		µs		6
Overcurrent protection retry time	tRETRY		1.2		ms		6
Junction-to-ambient thermal resistance	RθJA		67.7		°C/W	DW (SOIC) 20 pins	5
Junction-to-case (top) thermal resistance	RθJC(top)		32.9		°C/W	DW (SOIC) 20 pins	5
Junction-to-board thermal resistance	RθJB		35.4		°C/W	DW (SOIC) 20 pins	5
Junction-to-top characterization parameter	ψJT		8.2		°C/W	DW (SOIC) 20 pins	5
Junction-to-board characterization parameter	ψJB		34.9		°C/W	DW (SOIC) 20 pins	5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		to more efficiently remove heat from the device. The two center leads on each side of the package should be connected together to as large a copper area on the PCB as is possible to remove heat from t	16

CAD (KiCad official)

Symbol: DRV8805DWR
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20-300mil (KiCad packages3D, STEP)
3D model files: drv8805dwr-etched.step / drv8805dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8805dwr.step / drv8805dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (29 pp, sha256 9b6a668592ad69c8, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DRV8805DWR

Verified DRV8805DWR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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