A96G174FDN from ABOV Semicon, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Power supply pin, operating range 1.8V to 5.5V.
2	P00	bidirectional	Port 0 bit 0 I/O with pull-up, shared with AN3 ADC input ch-3, EC0 Timer 0 event capture input, DSDA OCD debugger data I/O and SS USART slave select.
3	P01	bidirectional	Port 0 bit 1 I/O with pull-up, shared with AN4 ADC input ch-4, DSCL OCD debugger clock input and SDA I2C data.
4	P02	bidirectional	Port 0 bit 2 I/O, shared with RESETB active-low reset input with pull-up on A96G174, EINT0 external interrupt ch-0 and SCL I2C clock.
5	P03	bidirectional	Port 0 bit 3 I/O, shared with AN5 ADC input ch-5, T0O Timer 0 interval output and PWM0O Timer 0 PWM output.
6	P04	bidirectional	Port 0 bit 4 I/O, shared with AN6 ADC input ch-6, T2O Timer 2 interval output and PWM2O Timer 2 PWM output.
7	P05	bidirectional	Port 0 bit 5 I/O, shared with AN7 ADC input ch-7 and SCK USART external clock input/output.
8	P06	bidirectional	Port 0 bit 6 I/O, shared with AN8 ADC input ch-8, MOSI(TXD) USART transmit/SPI MOSI and PWM1OB Timer 1 complementary PWM output.
9	P07	bidirectional	Port 0 bit 7 I/O, shared with AN9 ADC input ch-9, MISO(RXD) USART receive/SPI MISO, T1O Timer 1 interval output and PWM1O Timer 1 PWM output.
10	P10	bidirectional	Port 1 bit 0 I/O, shared with AN10 ADC input ch-10.
11	P11	bidirectional	Port 1 bit 1 I/O, shared with T2O Timer 2 interval output, PWM2O Timer 2 PWM output and SDA I2C data.
12	P12	bidirectional	Port 1 bit 2 I/O, shared with T1O Timer 1 interval output, PWM1O Timer 1 PWM output and SS USART slave select.
13	P13	bidirectional	Port 1 bit 3 I/O, shared with AN11 ADC input ch-11, EINT1 external interrupt ch-1, EC1 Timer 1 event capture input and XCK USART clock.
14	P14	bidirectional	Port 1 bit 4 I/O, shared with AN12 ADC input ch-12 and TXD(MOSI) USART transmit/SPI MOSI.
15	P15	bidirectional	Port 1 bit 5 I/O, shared with AN13 ADC input ch-13, EINT2 external interrupt ch-2 and RXD(MISO) USART receive/SPI MISO.
16	P16	bidirectional	Port 1 bit 6 I/O, shared with AN14 ADC input ch-14 (RESETB function applies to A96S174 only).
17	P17	bidirectional	Port 1 bit 7 I/O, shared with AN0 ADC input ch-0 and PWM1OB Timer 1 PWM complementary output.
18	P20	bidirectional	Port 2 bit 0 I/O, shared with AN1 ADC input ch-1, T1O Timer 1 interval output and PWM1O Timer 1 PWM output.
19	P21	bidirectional	Port 2 bit 1 I/O, shared with AN2 ADC input ch-2.
20	VSS	power_in	Ground pin.

Key specifications

Parameter	Value
Manufacturer	ABOV Semicon
Package	SOP-20-300mil
Category	Embedded Processors & Controllers
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	-0.3		6.5	V		61
Voltage on any pin	VI	-0.3			V	Voltage on any pin with respect to VSS	61
Output voltage	VO	-0.3			V		61
Maximum output current sourced per I/O pin	IOH			10	mA	per I/O pin	61
Maximum total output current sourced	∑IOH			80	mA		61
Maximum output current sunk per I/O pin	IOL			80	mA	per I/O pin	61
Maximum total output current sunk	∑IOL			100	mA		61
Total power dissipation	PT			600	mW		61
Storage temperature	TSTG	-65		150	°C		61
Operating voltage	VDD	1.8		5.5	V	fX= 0.5 ~16MHz Internal RC	61
Operating temperature	TOPR	-40		85	°C	VDD=1.8~5.5V	61
Integral linear error	ILE	-8	4	8	LSB	AVDD = 5.0V; MCLK = 8MHz	62
Differential linearity error	DLE	-2	1	2	LSB		62
Offset error of top	EOT	-8	4	8	LSB		62
Offset error of bottom	EOB	-4	2	4	LSB		62
Conversion time	tCON	7.5			us	12-bit resolution, 8MHz	62
Analog input leakage current	IAN			2	uA	VDDREF=5.12V	62
ADC operating current (enabled)	IADC		1	2	mA	Enable, VDD=5.12V	62
ADC operating current (disabled)	IADC			0.1	uA	Disable	62
BGR reference voltage	VBGR	1.164	1.2	1.236	V	TA=+25°C	63
BGR reference voltage	VBGR	1.146	1.2	1.254	V	TA=-40°C ~ 85°C	63
RESET release level	VPOR			1.32	V		63
POR current	IPOR			0.2	uA		63
LVR/LVI detection level	VLVR/VLVI		1.61	1.75	V	VLVR/VLVI measured when voltage drops (falling level)	63
LVR/LVI detection level	VLVR/VLVI	1.63	1.77	1.91	V	VLVR/VLVI measured when voltage drops (falling level)	63
LVR/LVI detection level	VLVR/VLVI	1.96	2.13	2.3	V	VLVR/VLVI measured when voltage drops (falling level)	63
LVR/LVI detection level	VLVR/VLVI	2.26	2.46	2.66	V	VLVR/VLVI measured when voltage drops (falling level)	63
LVR/LVI detection level	VLVR/VLVI	3.28	3.56	3.84	V	VLVR/VLVI measured when voltage drops (falling level)	63
LVR/LVI hysteresis	△V		20	180	mV		63
LVR and LVI current (both enabled)	IBL		14	24	uA	Enable (Both), VDD=3V, RUN Mode	63
LVR and LVI current (one of two enabled)	IBL		10	18	uA	Enable (One of two), VDD=3V, RUN Mode	63
LVR and LVI current (both disabled)	IBL			0.1	uA	Disable (Both), VDD=3V	63
High internal RC oscillator tolerance		-1.5		1.5	%	TA = 0°C to +50°C; with 0.1uF bypass capacitor	64
High internal RC oscillator tolerance		-2		2	%	TA = -10°C to +70°C	64
High internal RC oscillator tolerance		-2.5		2.5	%	TA = -40°C to +85°C	64
Clock duty ratio	TOD	40	50	60	%		64
Stabilization time	THFS			100	us		64
IRC current (disabled)	IIRC			0.1	uA	Disable	64
Low internal RC oscillator frequency	fLSIRC	102	128	154	kHz	TA=-40°C ~ +85°C	64
Stabilization time	TLSIRC			1	ms		64
LSIRC current (disabled)	ILSIRC			0.1	uA	Disable	64
Output low voltage	VOL1			1	V	VDD=4.5V, IOL=10mA; all output ports except VOL2	65
Input high leakage current	IIH			1	uA	All input ports	65
Input low leakage current	IIL	-1			uA	All input ports	65
Pull-up resistor (input ports)	RPU1	25	50	100	kΩ	VI=0V, TA=25°C; all input ports; VDD=5.0V	65
Pull-up resistor (input ports)	RPU1	50	100	200	kΩ	VI=0V, TA=25°C; all input ports; VDD=3.0V	65
Pull-up resistor (RESETB)	RPU2	150	250	400	kΩ	VI=0V, TA=25°C; RESETB; VDD=5.0V	65
Pull-up resistor (RESETB)	RPU2	300	500	700	kΩ	VI=0V, TA=25°C; RESETB; VDD=3.0V	65
Supply current (RUN)	IDD1 (RUN)	0.7	2	4	mA	fXIN=16MHz, VDD=5V	65
Supply current (IDLE)	IDD2 (IDLE)	0.5	1.5	3	mA	fXIN=16MHz, VDD=5V	65
Supply current (IDLE, HSIRC)	IDD2 (IDLE)	0.5		3	mA	fHSIRC=16MHz, VDD=5V	65
Supply current (STOP, WDT off and LVR off)	IDD3 (STOP)		2	7	uA	STOP @ WDT off & LVR off, VDD=5.5V, TA=25°C	65
Supply current (STOP, WDT on)	IDD3 (STOP)		3	22	uA	STOP @ WDT on, VDD=5.5V, TA=25°C	65
RESETB input low width	tRSL	10			us	Input, VDD=5V	66
Interrupt input high width	tINTH	200			ns	All interrupt, VDD=5V	66
Interrupt input low width	tINTL	200			ns	All interrupt, VDD=5V	66
External counter input high pulse width	tECWH	200			ns	ECn, VDD = 5V (n= 0, 1, 3)	66
External counter input low pulse width	tECWL	200			ns	ECn, VDD = 5V (n= 0, 1, 3)	66
External counter rising transition time	tREC	20			ns	ECn, VDD = 5V (n= 0, 1, 3)	66
External counter falling transition time	tFEC	20			ns	ECn, VDD = 5V (n= 0, 1, 3)	66

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		intended for simple implementation of look-up tables. A 16-bit base register (either the PC or	26

CAD (KiCad official)

Symbol: A96G174FDN
Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: a96g174fdn-etched.step / a96g174fdn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a96g174fdn.step / a96g174fdn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ABOV Semicon datasheet (106 pp, sha256 721ab8c941eedaf1, retrieved 2026-11-04, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A96G174FDN

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3D Model

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Schematic Symbol

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