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CD4572UBM

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Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CD4572UBM

Texas Instruments · Logic Gates · SOIC-16

CD4572UBM from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 J output Output J = inverse of A, from inverter 1 (one of four identical inverters).
2 A input Input A of inverter 1; protected by CMOS protection network, input range -0.5 V to VDD+0.5 V.
3 K output Output K = inverse of B, from inverter 2.
4 B input Input B of inverter 2; input range -0.5 V to VDD+0.5 V.
5 L output Output L = NOT(C+D), output of the 2-input NOR gate.
6 C input NOR gate input C; input range -0.5 V to VDD+0.5 V.
7 D input NOR gate input D, positioned adjacent to VSS for easy use of the gate as an inverter.
8 VSS power_in Ground / negative supply terminal; all voltages are referenced to VSS.
9 M output Output M = inverse of E, from inverter 3.
10 E input Input E of inverter 3; input range -0.5 V to VDD+0.5 V.
11 N output Output N = inverse of F, from inverter 4.
12 F input Input F of inverter 4; input range -0.5 V to VDD+0.5 V.
13 P output Output P = NOT(G·H), output of the 2-input NAND gate.
14 G input NAND gate input G; input range -0.5 V to VDD+0.5 V.
15 H input NAND gate input H, positioned adjacent to VDD for easy use of the gate as an inverter.
16 VDD power_in Positive supply; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V relative to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4572UBM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd4572ubm-etched.step / cd4572ubm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4572ubm.step / cd4572ubm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 67f857581cd36942, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF