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Contents

README

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FT118

XTX · Motor Driver ICs · SOP-8

FT118 from XTX, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Pin 1 is a no-connect (floating) pin and should be left unconnected.
2 INA input Logic input A controls the H-bridge (PWM IN/IN mode), with VINH min 2.0 V, VINL max 0.6 V, recommended input range 0 to 5 V, and absolute maximum -0.3 V to 5.5 V.
3 INB input Logic input B controls the H-bridge (PWM IN/IN mode), with VINH min 2.0 V, VINL max 0.6 V, recommended input range 0 to 5 V, and absolute maximum -0.3 V to 5.5 V.
4 VDD power_in Power supply input with recommended range 2.4 V to 7.2 V and absolute maximum -0.3 V to 8.0 V; the bypass capacitor should be placed as close to the VDD pin as possible.
5 OUTB output Full-bridge output B drives the motor, with continuous output current limited to 1.35 A (SOP8) and peak current limited to 2.5 A (FT118).
6 AGND power_in Analog ground pin, which must be connected to the system ground.
7 PGND power_in Power ground pin for the H-bridge, which must be isolated from the motor ground routing in layout.
8 OUTA output Full-bridge output A drives the motor, with continuous output current limited to 1.35 A (SOP8) and peak current limited to 2.5 A (FT118).

Key specifications

Parameter Value
Manufacturer XTX
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage VDD 2.4 7.2 V 5
Standby current IDDST 1 uA INA=INB=L, no load 5
Operating current IDD 80 200 uA INA=INB=H, or INA=H & INB=L, or INA=L & INB=H, no load 5
Input high voltage VINH 2 V 5
Input low voltage VINL 0.6 V 5
High-level input current IINH 3 20 uA VDD=5V, VIN=5V 5
Internal pull-down resistance RIN 1.7 MΩ 5
Output on-resistance (SOP8), HS_PMOS+LS_NMOS Rds(on) 0.57 0.75 Ω ILOAD=0.5A, HS_PMOS+LS_NMOS 5
Operating voltage VDD 2.4 7.2 V 4
Input voltage VINA/INB 0 5 V 4
Output current, forward/reverse (SOP8) IOUT 0 1.35 A 4
Supply voltage VDD -0.3 8 V 4
Peak output current (FT118) IPEAK 0 2.5 A 4
Logic input voltage VINA/INB -0.3 5.5 V 4
Electrostatic discharge, human body model ESD 4000 V HBM 4
Operating temperature TOPR -40 85 °C 4
Storage temperature Tstg -65 150 °C 4
Junction temperature Tj 150 °C 4
Lead soldering temperature 260 °C 10 s 4
Thermal resistance, junction to ambient (SOP8) θJA 130 °C/W 4
Logic input current, high IINL 0 μA VDD=5V, VIN=0V 5

CAD (KiCad official)

  • Symbol: FT118
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ft118-etched.step / ft118-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft118.step / ft118.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XTX datasheet (11 pp, sha256 714a96044e3a43cd, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF