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HC32M140J8TA-TQFP48

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XHSC Microcontrollers (MCU/MPU/SOC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllershc32m140j8ta-tqfp48factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Contents

README

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HC32M140J8TA-TQFP48

XHSC · Microcontrollers (MCU/MPU/SOC) · TQFP-48(7x7)

HC32M140J8TA-TQFP48 from XHSC, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P03 bidirectional General-purpose I/O P03 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT00_1 and SCS60_1.
2 P04 bidirectional General-purpose I/O P04 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT01_1 and SCK6_1.
3 P05 bidirectional General-purpose I/O P05 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT02_1 and SOT6_1.
4 P06 bidirectional General-purpose I/O P06 (I/O circuit C: CMOS output, Schmitt input, LCD supply input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT03_1 and SIN6_1.
5 P07/NMIX/ADTG_1/EMII0/SCS50_0 bidirectional General-purpose I/O P07 (I/O circuit C); also serves as NMIX non-maskable interrupt input, EMII0 motor emergency-stop request input, ADTG_1, and SCS50_0.
6 P10/INT00_0/CAOUT/SCK5_0 bidirectional General-purpose I/O P10 (I/O circuit C); alternate functions INT00_0, CAOUT voltage comparator result output, and SCK5_0.
7 P11/INT01_0/VC_INP/SOT5_0 bidirectional General-purpose I/O P11 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT01_0, VC_INP comparator analog input, and SOT5_0.
8 P12/INT02_0/VC_INM/SIN5_0 bidirectional General-purpose I/O P12 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT02_0, VC_INM comparator analog input, and SIN5_0.
9 RSTB input Port reset input; reset is active when the input is low (circuit F: Schmitt input with pull-up about 52 kΩ).
10 XLI/P13/SOT5_2 input Low-speed oscillator input XLI for the 32.768 kHz clock (typical); when an external clock is used on XLI, the pin can otherwise serve as P13 or SOT5_2.
11 XLO/P14/SIN5_2 passive Low-speed oscillator output XLO for the 32.768 kHz crystal; when an external low-speed clock is applied to XLI, this pin can be used as P14 or SIN5_2.
12 DVSS power_in Digital ground, 0 V reference for DVCC (DVSS = AVSS = 0.0 V in the recommended operating conditions).
13 XHO/P15 passive High-speed oscillator output XHO for a 4 to 16 MHz crystal; when an external high-speed clock is applied to XHI, this pin can be used as P15.
14 XHI/P16 input High-speed oscillator input XHI for a 4 to 16 MHz crystal or external clock (4 to 48 MHz when an external clock is applied); pin can otherwise serve as P16.
15 MD/P20 input Mode select pin: low selects normal operating mode, high selects flash serial programming mode; the datasheet states it must be connected directly to DVCC or DVSS (circuit E: Schmitt input with internal pull-down).
16 P21/INT04_1/SCK4_1/TIOA3_1 bidirectional General-purpose I/O P21 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT04_1, SCK4_1, and TIOA3_1.
17 P22/INT05_1/SOT4_1/TIOB3_1 bidirectional General-purpose I/O P22 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT05_1, SOT4_1, and TIOB3_1.
18 P23/INT06_1/SIN4_1/TIOB2_1 bidirectional General-purpose I/O P23 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT06_1, SIN4_1, and TIOB2_1.
19 P24/INT07_1/CTS4_1/TIOA2_1 bidirectional General-purpose I/O P24 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT07_1, CTS4_1, and TIOA2_1.
20 SWCLK/P30/SIN4_0/TIOB3_0 bidirectional Serial-wire debug clock SWCLK (also general-purpose I/O P30, SIN4_0, TIOB3_0); if used as GPIO or another peripheral it must be set to output-only and never to input function.
21 SWDIO/P31/SOT4_0/TIOA3_0 bidirectional Serial-wire debug data input/output SWDIO (also general-purpose I/O P31, SOT4_0, TIOA3_0); if used as GPIO or another peripheral it must be set to output-only and never to input function.
22 P32/INT03_0/SCK4_0/TIOA2_2 bidirectional General-purpose I/O P32 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA, optional open-drain); alternate functions INT03_0, SCK4_0, and TIOA2_2.
23 DVSS power_in Digital ground, 0 V reference for DVCC.
24 VDD power_out Internal regulator output for the digital core; a stabilizing capacitor of about 4.7 µF must always be connected to this pin (recommended filter capacitor CS 1 to 10 µF).
25 DVCC power_in Digital supply voltage, 2.7 V to 5.5 V (recommended operating range); the datasheet recommends about 0.1 µF ceramic decoupling between DVCC and DVSS near the device.
26 P40/ADTG_0/OPAP0/CTS4_0/TIOB2_0 bidirectional General-purpose I/O P40 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions ADTG_0, OPAP0 op-amp channel 0 input/output, CTS4_0, and TIOB2_0.
27 P41/OPAM0/RTS4_0/TIOA2_0 bidirectional General-purpose I/O P41 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions OPAM0 op-amp channel 0 input/output, RTS4_0, and TIOA2_0.
28 P42/OPAO0/SCS41_0/TIOB1_0 bidirectional General-purpose I/O P42 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions OPAO0 op-amp channel 0 input/output, SCS41_0, and TIOB1_0.
29 P43/INT04_0/A0/SCS40_0/TIOA1_0 bidirectional General-purpose I/O P43 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT04_0, A0 ADC analog input channel 0, SCS40_0, and TIOA1_0.
30 P44/INT05_0/A1/OPAP1 bidirectional General-purpose I/O P44 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT05_0, A1 ADC analog input channel 1, and OPAP1 op-amp channel 1 input/output.
31 P45/INT06_0/A2/OPAM1/TIOB0_0 bidirectional General-purpose I/O P45 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT06_0, A2 ADC analog input channel 2, OPAM1 op-amp channel 1 input/output, and TIOB0_0.
32 P46/INT07_0/A3/OPAO1/TIOA0_0 bidirectional General-purpose I/O P46 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT07_0, A3 ADC analog input channel 3, OPAO1 op-amp channel 1 output, and TIOA0_0.
33 P47/INT08_1/A4/TIOB0_1 bidirectional General-purpose I/O P47 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT08_1, A4 ADC analog input channel 4, and TIOB0_1.
34 P50/INT09_1/A5/TIOA0_1 bidirectional General-purpose I/O P50 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT09_1, A5 ADC analog input channel 5, and TIOA0_1.
35 P51/INT10_1/A6/TIOB1_1 bidirectional General-purpose I/O P51 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT10_1, A6 ADC analog input channel 6, and TIOB1_1.
36 P52/INT11_1/A7/TIOA1_1 bidirectional General-purpose I/O P52 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT11_1, A7 ADC analog input channel 7, and TIOA1_1.
37 P60/INT08_0/A8/EXCK0_0/CTS6_0/TIOB1_2 bidirectional General-purpose I/O P60 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT08_0, A8 ADC analog input channel 8, EXCK0_0, CTS6_0, and TIOB1_2.
38 P61/INT09_0/A9/Avref/RTS6_0/TIOB2_2 bidirectional General-purpose I/O P61 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT09_0, A9 ADC analog input channel 9, Avref ADC reference voltage input, RTS6_0, and TIOB2_2.
39 P62/INT12_1/SCS50_1/TIOB0_2 bidirectional General-purpose I/O P62 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT12_1, SCS50_1, and TIOB0_2.
40 P63/INT13_1/SCK5_1/TIOA0_2 bidirectional General-purpose I/O P63 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT13_1, SCK5_1, and TIOA0_2.
41 P64/INT14_1/SOT5_1 bidirectional General-purpose I/O P64 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT14_1 and SOT5_1.
42 P65/INT15_1/EXCK0_1/SIN5_1/IRCO_1 bidirectional General-purpose I/O P65 (I/O circuit B: CMOS output, Schmitt input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT15_1, EXCK0_1, SIN5_1, and IRCO_1 internal high-speed oscillator clock output.
43 P70/INT10_0/A10/PWM00/SCK6_0 bidirectional General-purpose I/O P70 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT10_0, A10 ADC analog input channel 10, PWM00 motor-control PWM output 0, and SCK6_0.
44 P71/INT11_0/A11/PWM01/SOT6_0 bidirectional General-purpose I/O P71 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT11_0, A11 ADC analog input channel 11, PWM01 motor-control PWM output 1, and SOT6_0.
45 P72/INT12_0/A12/PWM02/SIN6_0 bidirectional General-purpose I/O P72 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT12_0, A12 ADC analog input channel 12, PWM02 motor-control PWM output 2, and SIN6_0.
46 P73/INT13_0/A13/PWM03/SCS62_0/IRCO_0 bidirectional General-purpose I/O P73 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT13_0, A13 ADC analog input channel 13, PWM03 motor-control PWM output 3, SCS62_0, and IRCO_0 internal high-speed oscillator clock output.
47 P74/INT14_0/A14/PWM04/SCS61_0 bidirectional General-purpose I/O P74 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT14_0, A14 ADC analog input channel 14, PWM04 motor-control PWM output 4, and SCS61_0.
48 P75/INT15_0/A15/PWM05/SCS60_0 bidirectional General-purpose I/O P75 (I/O circuit A: CMOS output, Schmitt input, analog input, pull-up about 52 kΩ, IOH -5 mA / IOL 5 mA); alternate functions INT15_0, A15 ADC analog input channel 15, PWM05 motor-control PWM output 5, and SCS60_0.

Key specifications

Parameter Value
Manufacturer XHSC
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (DVCC and AVCC) VCC -0.3 5.8 V Referenced to DVSS=0 V (*1); DVCC not below DVSS-0.3 V (*2) 39
Input voltage VI -0.3 5.8 V Referenced to DVSS=0 V (*1) 39
Output voltage VO -0.3 5.8 V Referenced to DVSS=0 V (*1) 39
L-level maximum output current, 12 mA-type IO IOL 12.8 mA Peak, single pin (*3) 39
L-level maximum output current, 5 mA-type IO IOL 5.1 mA Peak, single pin (*3) 39
L-level average output current IOLAV 5 mA Averaged over 100 ms, single pin (*4) 39
L-level total maximum output current ΣIOL 100 mA All pins 39
L-level total average output current ΣIOLAV 50 mA Averaged over 100 ms, all pins (*5) 39
H-level maximum output current, 12 mA-type IO IOH 12.8 mA Peak, single pin (*3) 39
H-level maximum output current, 5 mA-type IO IOH 5.1 mA Peak, single pin (*3) 39
H-level average output current IOHAV 5 mA Averaged over 100 ms, single pin (*4) 39
H-level total maximum output current ΣIOH 100 mA All pins 39
H-level total average output current ΣIOHAV 50 mA Averaged over 100 ms, all pins (*5) 39
Power dissipation PD 165 mW 39
Storage temperature TSTG -55 150 °C 39
Supply voltage DVCC 2.7 5.5 V DVSS=AVSS=0.0 V 40
Supply voltage (analog) AVCC 2.7 5.5 V Must be the same as DVCC (*3) 40
Filter capacitor CS 1 10 μF Voltage regulator (*1) 40
Operating temperature Ta -40 85 °C 40
Supply current, normal run, PLL mode 48 MHz Icc 11.8 12.4 mA PLL mode, 48 MHz, NOP from flash, CKENx stops all peripheral clocks 41
Supply current, normal run, internal 4 MHz oscillator Icc 1.5 2.1 mA Internal HS oscillator mode, 4 MHz, NOP, CKENx stops peripheral clocks 41
Supply current, normal run, external 4 MHz crystal Icc 1.5 2.2 mA External HS crystal mode, 4 MHz, internal HS oscillator stopped 41
Supply current, normal run, 48 MHz external clock Icc 10.4 10.8 mA External 48 MHz clock input, internal HS oscillator stopped, PCLK1 stopped 41
Supply current, normal run, 32.768 kHz external LS crystal Icc 492 858 μA External LS crystal mode, 32.768 kHz, CKENx stops peripheral clocks 41
Supply current, normal run, internal 32 kHz oscillator Icc 503 853 μA Internal LS oscillator mode, 32 kHz, CKENx stops peripheral clocks 41
Supply current, CPU sleep, PLL mode 48 MHz Iccs 2.4 3 mA PLL mode, 48 MHz, CKENx stops peripheral clocks 41
Supply current, CPU sleep, internal 4 MHz oscillator Iccs 0.7 1.3 μA Internal HS oscillator mode, 4 MHz, CKENx stops peripheral clocks 41
Supply current, CPU sleep, external 4 MHz crystal Iccs 0.9 1.7 μA External HS crystal mode, 4 MHz, CKENx stops peripheral clocks 41
H-level input voltage VIH 3.15 V Hysteresis input, MODE pin 44
L-level input voltage VIL 1.35 V Hysteresis input, MODE pin 44
H-level output voltage, 5 mA-type IO VOH 3.7 V IOH = -5 mA 44
H-level output voltage, 12 mA-type IO VOH 3.7 V IOH = -12 mA 44
Input leakage current IIL -1 1 μA 44
Pull-up resistance RPU 22 63 kΩ Pull-up pins, VIN = 0 44
Input capacitance CIN 10 pF Pins other than DVCC, DVSS 44
Input frequency, external high-speed crystal FCH 4 48 MHz External high-speed crystal 45
Input frequency, external high-speed clock FCH 4 48 MHz External high-speed clock 45
Input clock period, external high-speed clock tCYLH 20.83 250 ns External high-speed clock 45
Input clock duty cycle, external high-speed clock PWH/Tcylh, PWL/Tcylh 45 55 % External high-speed clock 45
Input clock rise/fall time, external high-speed clock tCF, tCR 5 ns External high-speed clock 45
Internal circuit operating clock frequency, main clock FCM 48 MHz Main clock 45
Base clock frequency (HCLK/FCLK) FCC 48 MHz HCLK/FCLK 45
APB0 bus clock frequency FCP0 48 MHz APB0 bus clock (*2) 45
APB1 bus clock frequency FCP1 38 MHz APB1 bus clock (*2) 45
Internal circuit operating clock period, base clock tCYCC 20.83 ns HCLK/FCLK 45
Internal circuit operating clock period, APB0 bus clock tCYCP0 20.83 ns APB0 bus clock (*2) 45
Internal circuit operating clock period, APB1 bus clock tCYCP1 20.83 ns APB1 bus clock (*2) 45
Input frequency, external low-speed clock 1/tCYLL 32 50 kHz External low-speed clock 46
Input clock period, external low-speed clock tCYLL 20 31.25 μs External low-speed clock 46
Input clock duty cycle, external low-speed clock PWH/Tcyll, PWL/Tcyll 45 55 % External low-speed clock 46
SWDIO setup time tSWS 15 ns External load CL = 30 pF 69
SWDIO hold time tSWH 15 ns External load CL = 30 pF 69
SWDIO delay time tSWD 45 ns External load CL = 30 pF 69
ADC acquisition time TADCACQ 4 8 12 cycles 70
ADC conversion time TADCCONV 20 24 28 cycles 70
Effective number of bits ENOB 10 Bits 1 Msample/s 70
Differential nonlinearity DNL -1 1 LSB 70
Integral nonlinearity INL -3 3 LSB 70
Input clock frequency, external low-speed crystal (nominal) Fin 32.768 kHz Typical value; external low-speed crystal (*2) 40

CAD (KiCad official)

  • Symbol: HC32M140J8TA-TQFP48
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: hc32m140j8ta-tqfp48-etched.step / hc32m140j8ta-tqfp48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32m140j8ta-tqfp48.step / hc32m140j8ta-tqfp48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (92 pp, sha256 730ed257542d3f04, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF