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SAK-TC234LP-32F200N AC

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Infineon Technologies Microcontrollers (MCU/MPU/SOC), TQFP-144(16x16). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerssak-tc234lp-32f200n acfactory-2.0.0extractor-text
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SAK-TC234LP-32F200N AC

Infineon Technologies · Microcontrollers (MCU/MPU/SOC) · TQFP-144(16x16)

SAK-TC234LP-32F200N AC from Infineon Technologies, in a TQFP-144(16x16). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P02.0 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, SCU_REQ6, CCU60_CC60INA, CAN0_TXD, ERAY0_TXDA and CCU60_CC60 output.
2 P02.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, CAN0_RXDA, ERAY0_RXDA2, SCU_REQ14 and CCU60_COUT60.
3 P02.2 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, CCU60_CC61INA, ASCLIN1_TX, CAN2_TXD and ERAY0_TXDB.
4 P02.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input, ASCLIN1_RXG, CAN2_RXDB, ERAY0_RXDB2 and CCU60_COUT61.
5 P02.4 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_4 GTM input, QSPI3_SLSIA, CAN0_RXDD, CCU60_CC62INA, CAN10_TXD and ERAY0_TXENA.
6 P02.5 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_5 GTM input, QSPI3_MRSTA, SENT_SENT3C, CAN0_TXD, CAN11_TXD and ERAY0_TXENB.
7 P02.6 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_6 GTM input, QSPI3_MTSRA, SENT_SENT2C, CCU60_CCPOS0A, CCU61_T12HRB, GPT120_T3INA and VADC_EMUX00.
8 P02.7 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_7 GTM input, QSPI3_SCLKA, SENT_SENT1C, PMU_FDEST, QSPI3_SCLK output and CCU60_CC61.
9 P02.8 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, SENT_SENT0C, CCU60_CC62INC, QSPI3_SLSO5, ETH0_MDC output and CCU60_CC62.
10 VDD/VDDSB power_in Digital core power supply (1.3 V) per the pinout figure; the 144-pin function tables give no separate entry for this pin.
11 P00.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, CCU61_CTRAPA, ETH0_MDIOA, ASCLIN0_SCLK, ASCLIN0_TX, CAN1_TXD and ETH0_MDIO output.
12 P00.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, ASCLIN0_RXC, CAN1_RXDD, SENT_SENT0B, CCU60_CC60INB and CCU61_CC60INA.
13 P00.2 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, SENT_SENT1B, ASCLIN0_SCLK, CAN12_TXD and CCU61_COUT60.
14 P00.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include SENT_SENT2B, CCU60_CC61INB, CCU61_CC61INA, CAN11_RXDA, CAN12_RXDA, SENT_SPC2 and CCU61_CC61.
15 P00.4 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include SCU_REQ7, SENT_SENT3B, CAN10_TXD, VADC_G1BFL0, SENT_SPC3 and CCU61_COUT61.
16 P00.5 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include CCU60_CC62INB, CCU61_CC62INA, CAN10_RXDG, VADC_G1BFL1 and CCU61_CC62.
17 P00.6 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include CAN11_RXDG, VADC_G1BFL2, VADC_EMUX10 and CCU61_COUT62.
18 P00.7 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include CCU61_CC60INC, CCU61_CCPOS0A, CCU60_T12HRB, GPT120_T2INA, CAN11_TXD and VADC_G1BFL3.
19 P00.8 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include CCU61_CC61INC, CCU61_CCPOS1A, CCU60_T13HRB, GPT120_T2EUDA, CAN12_RXDG and QSPI3_SLSO6.
20 P00.9 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, CCU61_CC62INC, CCU61_CCPOS2A, GPT120_T4EUDA, QSPI3_SLSO7, ASCLIN0_RTS and CAN12_TXD.
21 P00.12 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input, ASCLIN0_CTSA and CCU61_COUT63.
22 VDD power_in Digital core power supply (1.3 V).
23 VDDP3 power_in Digital I/O power supply (3.3 V).
24 AN23/P41.11 input General-purpose input with analog input of VADC group 1 channel 11; pad class S (digital) and class D (analog), supplied from VDDM.
25 AN22/P41.10 input General-purpose input with analog input of VADC group 1 channel 10 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
26 AN21/P41.9 input General-purpose input with analog input of VADC group 1 channel 9 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
27 AN20/P41.8 input General-purpose input with analog input of VADC group 1 channel 8; pad class S/D, supplied from VDDM.
28 AN19/P41.7 input General-purpose input with analog input of VADC group 1 channel 7; pad class S/D, supplied from VDDM.
29 AN18/P41.6 input General-purpose input with analog input of VADC group 1 channel 6; pad class S/D, supplied from VDDM.
30 AN17/P41.5 input General-purpose input with analog input of VADC group 1 channel 5; pad class S/D, supplied from VDDM.
31 AN16/P41.4 input General-purpose input with analog input of VADC group 1 channel 4; pad class S/D, supplied from VDDM.
32 AN15/P41.3 input General-purpose input with analog input of VADC group 1 channel 3 (with pull-down diagnostics); pad class S/D, supplied from VDDM.
33 AN14/P41.2 input General-purpose input with analog input of VADC group 1 channel 2 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
34 AN13/P41.1 input General-purpose input with analog input of VADC group 1 channel 1 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
35 AN12/P41.0 input General-purpose input with analog input of VADC group 1 channel 0; pad class S/D, supplied from VDDM.
36 AN11/P40.11 input General-purpose input with analog input of VADC group 0 channel 11; pad class S/D, supplied from VDDM. Alternates include SENT_SENT0A and CCU60_CCPOS0D.
37 AN10/P40.10 input General-purpose input with analog input of VADC group 0 channel 10 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
38 AN9/P40.9 input General-purpose input with analog input of VADC group 0 channel 9 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
39 AN8/P40.8 input General-purpose input with analog input of VADC group 0 channel 8; pad class S/D, supplied from VDDM.
40 AN7/P40.7 input General-purpose input with analog input of VADC group 0 channel 7 (with pull-down diagnostics); pad class S/D, supplied from VDDM.
41 VAGND power_in Negative analog reference voltage 0 for the VADC.
42 VAREF power_in Positive analog reference voltage 0 for the VADC.
43 VSSM power_in Analog ground for VDDM.
44 VDDM power_in ADC power supply (5.0 V).
45 AN6/P40.6 input General-purpose input with analog input of VADC group 0 channel 6; pad class S/D, supplied from VDDM.
46 AN5/P40.5 input General-purpose input with analog input of VADC group 0 channel 5; pad class S/D, supplied from VDDM.
47 AN4/P40.4 input General-purpose input with analog input of VADC group 0 channel 4; pad class S/D, supplied from VDDM.
48 AN3/P40.3 input General-purpose input with analog input of VADC group 0 channel 3; pad class S/D, supplied from VDDM.
49 AN2/P40.2 input General-purpose input with analog input of VADC group 0 channel 2 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
50 AN1/P40.1 input General-purpose input with analog input of VADC group 0 channel 1 (with multiplexer diagnostics); pad class S/D, supplied from VDDM.
51 AN0/P40.0 input General-purpose input with analog input of VADC group 0 channel 0; pad class S/D, supplied from VDDM.
52 P34.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternate output TOM1_12 GTM_TOUT.
53 P34.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TOM1_13, ASCLIN0_TX, CAN0_TXD and IOM monitor/reference inputs.
54 P34.2 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN0_RXD, CAN0_RXDG and TOM1_14 GTM_TOUT.
55 P34.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_CTSB input, TOM1_15 GTM_TOUT and QSPI2_SLSO10.
56 P33.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_4 GTM input, IOM_PIN0, TOM0_4 GTM_TOUT and VADC_G1BFL0.
57 P33.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_5 GTM input, IOM_PIN1, TOM0_5 GTM_TOUT, VADC_EMUX02 and VADC_G1BFL1.
58 P33.2 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_6 GTM input, IOM_PIN2, TOM0_6 GTM_TOUT, VADC_EMUX01 and CCU61_COUT63.
59 P33.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_7 GTM input, IOM_PIN3, TOM0_7 GTM_TOUT, VADC_EMUX00 and CCU61_CC60.
60 P33.4 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, CCU61_CTRAPC, IOM_PIN4, TOM0_0 GTM_TOUT and VADC_EMUX12.
61 P33.5 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, CCU61_CCPOS2C, GPT120_T4EUDB, IOM_PIN5, QSPI0_SLSO7 and VADC_EMUX11.
62 P33.6 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, ASCLIN1_RXF, CCU61_CCPOS1C, GPT120_T2EUDB, CAN10_RXDH, IOM_PIN6, ASCLIN1_TX and HSM_HSM1.
63 P33.7 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input, CAN0_RXDE, SCU_REQ8, GPT120_T2INB, IOM_PIN7, CAN10_TXD and HSM_HSM2.
64 P33.8 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_4 GTM input, SCU_EMGSTOPA, IOM_PIN8, QSPI3_SLSO2, CAN0_TXD and SMU_FSP output.
65 P33.9 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, QSPI3_HSICINA, IOM_PIN9, QSPI3_SLSO1 and CCU61_CC62.
66 P33.10 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, QSPI3_SLSIC, QSPI3_HSICINB, IOM_PIN10, QSPI1_SLSO6 and GTM_CLK1 output.
67 P33.11 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, QSPI3_SCLKD, SCU_REQ17, IOM_PIN11, ASCLIN1_SCLK and SMPS_DCDCSYNC output.
68 P33.12 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, QSPI3_MTSRD, IOM_PIN12, ASCLIN1_TX and QSPI3_MTSR.
69 VDDP3 power_in Digital I/O power supply (3.3 V); also supplies the Flash 3.3 V.
70 VDD power_out Digital core power supply (1.3 V); this pin is the output of EVR13.
71 VCAP0 passive Pin named VCAP0 in the pinout figure; the datasheet gives no function description for this package.
72 VCAP1 passive Pin named VCAP1 in the pinout figure; the datasheet gives no function description for this package.
73 P23.1 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_6 GTM input, TOM0_6 GTM_TOUT, ASCLIN1_RTS, QSPI3_SLSO13, GTM_CLK0 output and SCU_EXTCLK0/1 outputs.
74 P22.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, QSPI3_MTSRE, TOM0_9 GTM_TOUT and QSPI3_MTSR output.
75 P22.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, QSPI3_MRSTE, IOM_MON2_3 and QSPI3_MRST output.
76 P22.2 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input, QSPI3_SLSID, TOM0_11 GTM_TOUT and QSPI3_SLSO12 output.
77 P22.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_4 GTM input, QSPI3_SCLKE, TOM0_12 GTM_TOUT and QSPI3_SCLK output.
78 P22.4 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TOM0_7N GTM_TOUT and QSPI0_SLSO12 output.
79 VDD power_in Digital core power supply (1.3 V).
80 VSS power_in Digital ground (0 V).
81 XTAL1 input Main oscillator/PLL/clock generator input, pad supplied from VDDP3.
82 XTAL2 output Main oscillator/PLL/clock generator output, pad supplied from VDDP3.
83 VDDP3 power_in Digital I/O power supply (3.3 V).
84 P21.2 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, SCU_EMGSTOPB, TOM0_0 GTM_TOUT and ETH0_MDC output.
85 P21.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, ETH0_MDIOD and ETH0_MDIO output.
86 P21.4 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, TOM0_2 and TOM1_2 GTM_TOUT outputs.
87 P21.5 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input and TOM0_3 GTM_TOUT output.
88 P21.6/TDI bidirectional GPIO, pad class A1 (3.3 V) with pull-up during reset; TDI JTAG input, also TIM0_4 GTM input, OCDS_TGI2 and GPT120_T5EUDA.
89 TMS/DAP1 bidirectional Debug interface pin TMS/DAP1 (device access port line 1), pad class A1+ with pull-down during reset.
90 P21.7/TDO/DAP2 bidirectional GPIO, pad class A1+ with pull-up during reset; TDO JTAG output and OCDS_DAP2 input/output, also TIM0_5 GTM input and GPT120_T5INA.
91 TRST input JTAG module reset/enable input (input only, pull-down during reset).
92 TCK/DAP0 input OCDS input and device access port line 0 (input only, pull-down during reset).
93 P20.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_6 GTM input, SCU_REQ9, OCDS_TGI0, GPT120_T6EUDA, CAN11_RXDC and OCDS_TGO0 output.
94 P20.2/TESTMODE input Input only with pull-up during reset; factory test mode enable.
95 P20.3 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_4 GTM input, GPT120_T6INA, QSPI0_SLSO9, QSPI2_SLSO9 and CAN12_TXD.
96 ESR1 bidirectional SCU input/output and EVR wake-up pin (EVRWUP), pad class A1+ with pull-up during reset.
97 PORST input Power-on reset input (input only, pull-down during reset) with additional strong pull-down in case of power fail.
98 ESR0 bidirectional SCU input/output and EVR wake-up pin (EVRWUP), pad class A1+ open-drain; driven low during reset.
99 VDD power_in Digital core power supply (1.3 V).
100 P20.6 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_6 GTM input, TOM1_10 GTM_TOUT, ASCLIN1_RTS, QSPI0_SLSO8 and QSPI2_SLSO8.
101 P20.7 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_7 GTM input, ASCLIN1_CTSA, CAN0_RXDB and CCU61_COUT63.
102 P20.8 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_7 GTM input, ASCLIN1_SLSO, QSPI0_SLSO0, CAN0_TXD, SCU_WDT0LCK and CCU61_CC60.
103 P20.9 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_RXC, QSPI0_SLSIB, SCU_REQ11, CAN12_RXDE, SCU_WDTSLCK and CCU61_CC61.
104 P20.10 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_TX, QSPI0_SLSO6, QSPI2_SLSO7, CAN12_TXD, ASCLIN1_SCLK and CCU61_CC62.
105 P20.11 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI0_SCLKA, QSPI0_SCLK output, CAN11_TXD and CCU61_COUT60.
106 P20.12 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include QSPI0_MRSTA, CAN11_RXDH, IOM_PIN13, QSPI0_MRST, QSPI0_MTSR and CCU61_COUT61.
107 P20.13 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI0_SLSIA, CAN12_RXDH, IOM_PIN14, QSPI0_SCLK output and CCU61_COUT62.
108 P20.14 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI0_MTSRA, IOM_PIN15, QSPI0_MTSR output and CAN12_TXD.
109 P15.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_TX, QSPI0_SLSO13, CAN2_TXD and ASCLIN1_SCLK.
110 P15.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_RXA, QSPI2_SLSIB, CAN2_RXDA, SCU_REQ16, SCU_EVRWUPB (analog) and ASCLIN1_TX.
111 P15.2 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI2_MRSTE, QSPI2_SLSIA, QSPI2_HSICINA, ASCLIN0_TX, CAN1_TXD and ASCLIN0_SCLK.
112 P15.3 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include ASCLIN0_RXB, QSPI2_SCLKA, QSPI2_HSICINB, CAN1_RXDA, ASCLIN0_TX and QSPI2_SCLK output.
113 P15.4 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI2_MRSTA, SCU_REQ0, ASCLIN1_TX, QSPI2_MRST output and CCU60_CC62.
114 P15.5 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_RXB, QSPI2_MTSRA, SCU_REQ13, ASCLIN1_TX, QSPI2_MTSR output and CCU60_CC61.
115 P15.6 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, QSPI2_MTSRB, QSPI2_MTSR output, QSPI2_SCLK output and CCU60_CC60.
116 P15.7 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, QSPI2_MRSTB, QSPI2_MRST output and CCU60_COUT60.
117 P15.8 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, QSPI2_SCLKB, SCU_REQ1, QSPI2_SCLK output and CCU60_COUT61.
118 P14.0/Bootloader bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; labelled Bootloader in the pinout; alternates include TIM0_3 GTM input, ASCLIN0_TX, ERAY0_TXDA, ERAY0_TXDB and CAN1_TXD.
119 P14.1/Bootloader bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; labelled Bootloader in the pinout; alternates include TIM0_4 GTM input, ASCLIN0_RXA, CAN1_RXDB, SCU_REQ15 and SCU_EVRWUPA (analog).
120 P14.2 bidirectional GPIO, pad class A1 (3.3 V) with pull-up during reset; alternates include TIM0_5 GTM input, SCU_HWCFG2_EVR13, IOM_REF1_15 and QSPI2_SLSO1 output.
121 P14.3 bidirectional GPIO, pad class A1 (3.3 V) with pull-up during reset; alternates include TIM0_6 GTM input, SCU_REQ10, SCU_HWCFG3_BMI, QSPI2_SLSO3 and ASCLIN1_SLSO.
122 P14.4 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_7 GTM input, TOM0_7 GTM_TOUT and IOM_REF2_8.
123 P14.5 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, TOM0_0 GTM_TOUT, IOM_REF2_11 and ERAY0_TXDB output.
124 P14.6 bidirectional GPIO, pad class A1+ (3.3 V) with pull-up during reset; alternates include TIM0_1 GTM input, SCU_HWCFG0_DCLDO, QSPI0_MRSTD, QSPI2_SLSO2 and ERAY0_TXENB.
125 P14.7 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_0 GTM input, ERAY0_RXDB0, TOM0_0 GTM_TOUT, ASCLIN0_RTS and QSPI2_SLSO4.
126 VDDP3 power_in Digital I/O power supply (3.3 V); this pin also supplies the Flash 3.3 V.
127 P14.8 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include ASCLIN1_RXD, CAN2_RXDD, ERAY0_RXDA0 and TOM0_2 GTM_TOUT.
128 P13.0 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include CCU60_CTRAPA, GPT120_T6EUDB, QSPI2_SCLK output, ETH0_TXER and CAN10_TXD.
129 P13.1 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include CCU60_CCPOS0C, GPT120_T3INB, CAN10_RXDB and ETH0_TXCLKC.
130 P13.2 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include CCU60_CCPOS1C, GPT120_T3EUDB, GPT120_CAPINA, CAN11_TXD and ETH0_TXD3.
131 P13.3 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include CCU60_CCPOS2C, GPT120_T4INB, CAN11_RXDB, QSPI2_MTSR output and ETH0_TXD2.
132 P11.2 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TOM0_8 GTM_TOUT, QSPI0_SLSO5, QSPI1_SLSO5, CCU61_COUT63, ETH0_TXD1 and CCU60_COUT63.
133 P11.3 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI1_MRSTB, QSPI1_MRST output, ERAY0_TXDA, CCU61_COUT62, ETH0_TXD0 and CCU60_COUT62.
134 P11.6 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI1_SCLKB, QSPI1_SCLK output, ERAY0_TXENB, ERAY0_TXENA, ETH0_TXEN and CCU60_COUT61.
135 P11.9 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include QSPI1_MTSRB, ERAY0_RXDA1, ETH0_RXD1A, QSPI1_MTSR output, CCU61_COUT60 and CCU60_COUT60.
136 P11.8 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include QSPI1_MTSRC, ETH0_RXD2A, QSPI1_SLSO10 and QSPI1_MTSR output.
137 P11.10 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include ASCLIN1_RXE, ERAY0_RXDB1, SCU_REQ12, CAN12_RXDD, ETH0_RXD0A and CCU60_CC62.
138 P11.11 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include ETH0_RXDVA, ETH0_CRSDVA, ETH0_CRSB, QSPI0_SLSO4, CCU61_CC61 and CCU60_CC61.
139 P11.12 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include ETH0_REFCLK, ETH0_RXCLKA, ETH0_TXCLKB, ASCLIN1_TX, GTM_CLK2 output, ERAY0_TXDB and CCU60_CC60.
140 P10.1 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_1 GTM input, QSPI1_MRSTA, GPT120_T5EUDB, ETH0_CRSC, QSPI1_MTSR and QSPI1_MRST outputs.
141 P10.2 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, QSPI1_SCLKA, CAN2_RXDE, SCU_REQ2, GPT120_T6INB, ETH0_COLB and QSPI1_SCLK output.
142 P10.3 bidirectional GPIO, pad class A1+ (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input, QSPI1_MTSRA, SCU_REQ3, GPT120_T5INB, ETH0_RXERC, QSPI1_MTSR output and CAN2_TXD.
143 P10.5 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_2 GTM input, SCU_HWCFG4, CAN10_RXDA, ETH0_RXD3B, QSPI3_SLSO8 output and GPT120_T6OUT.
144 P10.6 bidirectional GPIO, pad class A1 (3.3 V), High-Z at reset; alternates include TIM0_3 GTM input, QSPI3_MTSRB, SCU_HWCFG5, QSPI3_MTSR output, GPT120_T3OUT and CAN10_TXD.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TQFP-144(16x16)
Category Embedded Processors & Controllers
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TST -65 170 °C upto 65h @ TJ = 150°C; upto 15h @ TJ = 170°C 180
Voltage at VDD power supply pins with respect to VSS VDD 1.9 V 180
Voltage at VDDP3 power supply pins with respect to VSS VDDP3 4.43 V 180
Voltage at VDDM power supply pin with respect to VSS VDDM 7 V 180
Voltage on all analog and class S input pins with respect to VSS VIN -0.5 7 V 180
Voltage on all other input pins with respect to VSS VIN -0.5 V Whatever is lower of VDDP3 + 0.6 and 4.23 (max printed as formula) 180
Input current on any pin during overload condition IIN -10 10 mA 180
Absolute maximum sum of all input circuit currents during overload condition ΣIIN -100 100 mA 180
SRI frequency fSRI 200 MHz 183
Max System Frequency fMAX 200 MHz 183
CPU0 Frequency fCPU0 200 MHz 183
PLL output frequency fPLL 20 200 MHz 183
PLL_ERAY output frequency fPLLERAY 20 160 MHz 183
SPB frequency fSPB 100 MHz 183
GTM frequency fGTM 100 MHz 183
ERAY frequency fERAY 80 MHz 183
Absolute sum of short circuit currents of the device ΣISC_D 100 mA 184
Ambient Temperature TA -40 125 °C valid for all SAK products 184
Junction Temperature TJ -40 150 °C valid for all SAK products 184
Core Supply Voltage VDD 1.17 1.3 1.43 V Only required if externally supplied 184
ADC analog supply voltage VDDM 2.97 5 5.5 V 184
Voltage to ensure defined pad states VDDPPA 0.72 V 184
Digital supply voltage for GPIO pads and EVR VDDP3 2.97 3.3 3.63 V All VDDP3 pins shall be connected together externally on the PCB. 184
Pin capacitance (digital inputs/outputs) CIO 6 10 pF 185
Spike filter always blocked pulse duration tSF1 80 ns PORST only 185
Spike filter pass-through pulse duration tSF2 220 ns PORST only 185
PORST pad output current IPORST 10.1 mA VDDP3 = 3.0V; VPORST = 0.9V; TJ = 150°C; 185
Input Leakage Current Class A1 IOZA1 -400 400 nA (0.1VDDP3) < VIN < (0.9VDDP3) 185
Input Leakage Current Class A1 IOZA1 -475 475 nA (0.1VDDP3) < VIN < (0.9VDDP3); only vaild for P0.0 185
Input Leakage Current Class A1 IOZA1 -800 800 nA else 185
Pull-down current class A1 pads IPDLA1 120 µA VIHmin (printed as /120/) 185
Pull-down current class A1 pads IPDLA1 15 µA VILmax (printed as /15/) 185
Pull-up current class A1 pads IPUHA1 15 µA VIHmin (printed as /15/) 185
Pull-up current class A1 pads IPUHA1 120 µA VILmax (printed as /120/) 185
On-Resistance of the A1 pad, medium driver RDSONA1M 50 125 200 Ohm IOH=2mA; IOL=2mA 185
On-Resistance of the class A1 pad, weak driver RDSONA1W 250 500 800 Ohm IOH=0.5mA; IOL=0.5mA 185
Calibration reference accuracy TCALACC -1 1 °C calibration points @ TJ=-40°C and TJ=127°C 196
Temperature sensor range TSR -40 170 °C 196
Sum of IDD 1.3 V core and peripheral supply currents IDD 215 mA valid for Feature Package L, LC, LP, S, and SP; max power pattern 197
Sum of IDD 1.3 V core and peripheral supply currents IDD 160 mA valid for Feature Package L, LC, LP, S, and SP; real power pattern 197
Sum of all currents (incl. IDDP3RAIL+IDD+IDDM) IDDTOTL 200 mA valid for Feature Package L, LC, LP, S, and SP; real power pattern 198
Sum of all currents (SLEEP mode) ISLEEP 10 mA CPU is in idle, All peripherals in sleep, fSRI/SPB = 1 MHz; TJ = 55°C 198
Input voltage range VIN 2.97 3.63 V pass device=on chip 206
Output voltage operational range including load/line regulation and aging incase of LDO regulator VOUT 1.17 1.3 1.43 V pass device=on chip 206
Output VDD static voltage accuracy after trimming without dynamic load/line regulation with aging incase of LDO regulator VOUTT 1.275 1.3 1.325 V product load equal to IDD of max power pattern; either TJ≤150°C and pass device=on chip or TJ≤170°C and pass device=off chip 206
Output buffer capacitance on VOUT COUT 1.4 2.2 3 µF On chip pass device usage restricted to IDD < 230mA.; pass device=on chip 206
Primary undervoltage reset threshold for VDD VRST13 1.17 V pass device=on chip 206
VDDP3 primary undervoltage monitor accuracy after trimming VDDP3PRIUV 2.86 2.92 2.97 V 207
VDD primary undervoltage monitor accuracy after trimming VDDPRIUV 1.13 1.15 1.17 V 207
VDDP3 secondary supply monitor accuracy VDDP3MON 3.23 3.3 3.37 V SWDxxVAL VDDP3 monitoring threshold=3.3V=91h 207
VDD secondary supply monitor accuracy VDDMON 1.27 1.3 1.33 V EVR13xxVAL VDD monitoring threshold=1.3V=E4h 207
SMPS regulator static voltage output accuracy after trimming without dynamic load/line Regulation with aging VDDDCT 1.275 1.3 1.325 V VDDP3 > 2.97V; IDDDC < 230mA; fDCDC = 1MHz 207
Programmable switching frequency fDCDC 0.4 2 MHz 207
External output capacitor value COUTDC 6.5 10 13.5 µF IDDDC=230mA 208
Thermal resistance junction to case top (RQJCT), soldered exposed pad, internal pass device RQJCT 20.9 K/W with soldered exposed pad and internal pass device 234
Thermal resistance junction to case bottom (RQJCB), soldered exposed pad, internal pass device RQJCB 11.7 K/W with soldered exposed pad and internal pass device 234
Thermal resistance junction to ambient (RQJA), soldered exposed pad, internal pass device RQJA 30 K/W with soldered exposed pad and internal pass device 234
Thermal resistance junction to case top (RQJCT), soldered exposed pad, DCDC EVR RQJCT 11.7 K/W with soldered exposed pad and DCDC EVR 234
Thermal resistance junction to case bottom (RQJCB), soldered exposed pad, DCDC EVR RQJCB 2.8 K/W with soldered exposed pad and DCDC EVR 234

CAD (KiCad official)

  • Symbol: SAK-TC234LP-32F200N AC
  • Footprint: Package_QFP:TQFP-144_16x16mm_P0.4mm
  • 3D model: TQFP-144(16x16) (KiCad packages3D, STEP)
  • 3D model files: sak-tc234lp-32f200n-ac-etched.step / sak-tc234lp-32f200n-ac-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sak-tc234lp-32f200n-ac.step / sak-tc234lp-32f200n-ac.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (238 pp, sha256 7e515ee11e06c188, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF