MP1531DM-LF-Z from Monolithic Power Systems, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RDY	output	Open-drain active-low Regulators Not Ready output requiring an external 100kΩ pull-up; pulled low once startup completes and all FB voltages exceed 80% of threshold, goes high ~15µs after a fault, and the chip shuts down if the fault persists beyond ~6ms (C4 = 10nF).
2	FB1	input	Step-up converter feedback input (inverting input of the error amplifier); connect a resistive divider from the step-up output to set its voltage, regulating at 1.22V to 1.28V (1.25V typ).
3	COMP	passive	Step-up converter compensation node, the error amplifier output; connect a series RC network to compensate the control loop.
4	IN	power_in	Internal power input supplying the MP1531 from 2.7V to 5.5V; bypass IN to PGND with a 10µF or greater capacitor.
5	GND	power_in	Signal ground.
6	REF	power_out	1.25V reference voltage output; bypass to GND with 0.1µF or greater and connect to the low-side resistor of the negative linear regulator feedback string.
7	FB2	input	Negative linear regulator feedback input; connect the resistor string between GL and REF, with a regulation threshold of GND (0V ±25mV).
8	FB3	input	Positive linear regulator feedback input; connect the resistor string between GH and GND, with a regulation threshold of 1.25V.
9	EN	input	On/off control input: drive high to turn on, low to turn off (all outputs immediately disabled); connect to IN for automatic startup; rising threshold 1.6V, low level 0.3V.
10	GL	power_out	Negative linear regulator output supplying up to 10mA; bypass to GND with a 1µF or greater low-ESR ceramic capacitor.
11	IN2	power_in	Negative linear regulator input, driven by an inverting charge pump powered from SW; can go as low as -20V.
12	GH	power_out	Positive linear regulator output supplying up to 10mA; bypass to GND with a 1µF or greater low-ESR ceramic capacitor.
13	IN3	power_in	Positive linear regulator input, driven by a doubling, tripling or quadrupling charge pump from SW; can go as high as 38V.
14	PGND	power_in	Power ground, the source of the internal 250mΩ N-channel MOSFET switch; connect to GND as close to the MP1531 as possible.
15	SW	passive	Step-up converter power switch node, the drain of the internal 250mΩ N-channel MOSFET; connect the inductor from the input source to SW and a rectifier from SW to the main output (-0.3V to +25V).
16	CT	passive	Timing capacitor pin for soft-start, power-on sequencing and fault timer; a capacitor from CT to GND sets the delay periods (10nF gives 6ms).

Key specifications

Parameter	Value
Manufacturer	Monolithic Power Systems
Package	TSSOP-16
Category	Power Management (PMIC)
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Voltage Range	VIN	2.7		5.5	V	VIN = 5.0V, TA = +25C	3
IN Undervoltage Lockout Threshold	VUVLO		2.25	2.65	V	IN Rising	3
IN Shutdown Current			0.5	1	μA	VEN < 0.3V	3
IN Quiescent Current			1.2	1.6	mA	VEN > 2V, VFB1 = 1.4V	3
EN Input Low Voltage				0.3	V		3
EN Input High Voltage	VEN-HIGH	1.6			V	EN Rising	3
EN Input Bias Current				1	μA		3
Switching Frequency	fSW	200	250	300	kHz		3
Maximum Duty Cycle	DM	85	90		%		3
FB1, FB3 Regulation Voltage		1.22	1.25	1.28	V		3
FB2 Regulation Voltage		-25	0	25	mV		3
FB1, FB3 Input Bias Current		-100		100	nA	VFB1 = VFB3 = 1.25V	3
FB2 Input Bias Current		-100		100	nA	VFB2 = 0V	3
REF Regulation Voltage		1.22	1.25	1.28	V	IREF = 50μA	3
REF Load Regulation			1	1.2	%	0μA < IREF < 200μA	3
SW On Resistance			250		mΩ	VIN = 5V	3
SW On Resistance			400		mΩ	VIN = 3V	3
SW Current Limit	ILIM		0.5	0.65	A		3
SW Leakage Current			0.5	1	µA	VSW = 22V	3
GL Leakage Current				1	µA	VIN2 = -15V, VGL = GND	3
GH Leakage Current				1	µA	VIN3 = 25V, VGH = GND	3
IN Supply Voltage		-0.3		6	V		2
SW Voltage		-0.3		25	V		2
IN2, GL Voltage		-25		0.3	V		2
IN3, GH Voltage		-0.3		40	V		2
IN2 to IN3 Voltage		-0.3		60	V		2
All Other Pins		-0.3		6	V		2
Continuous Power Dissipation TSSOP16				1.4	W	TA = +25°C	2
Junction Temperature				125	°C		2
Lead Temperature				260	°C		2
Storage Temperature		-65		150	°C		2
Input Voltage		2.7		5.5	V		2
Main Output Voltage				22	V	VIN to 22V	2
IN2, GL Voltage		-20		0	V		2
IN3, GH Voltage		0		38	V		2
Maximum Junction Temp.	TJ			125	°C		2
Thermal Resistance TSSOP16 junction-to-ambient	θJA		90		°C/W	TSSOP16	2
Thermal Resistance TSSOP16 junction-to-case	θJC		30		°C/W	TSSOP16	2
IN Undervoltage Lockout Hysteresis			100		mV		3
EN Hysteresis			100		mV		3
Soft-Start Period			6		ms	C4 = 10nF	3
GL Dropout Voltage			0.15		V	VGL = -10V, IGL = 10mA	3
GH Dropout Voltage			0.5		V	VGH = 20V, IGH = 10mA	3
Thermal Shutdown			160		C		3

CAD (KiCad official)

Symbol: MP1531DM-LF-Z
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: mp1531dm-lf-z-etched.step / mp1531dm-lf-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp1531dm-lf-z.step / mp1531dm-lf-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Monolithic Power Systems datasheet (15 pp, sha256 620467760e8cb3fb, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MP1531DM-LF-Z

Verified MP1531DM-LF-Z

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README