component
A1326LLHLX-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Magnetic Sensors, SOT-23W. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA1326LLHLX-T
Allegro MicroSystems, LLC · Magnetic Sensors · SOT-23W
A1326LLHLX-T from Allegro MicroSystems, LLC, in a SOT-23W. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Input power supply (4.5 to 5.5 V operating, 8 V absolute maximum); tie to GND with a bypass capacitor (0.1 µF). |
| 2 | VOUT | output | Analog ratiometric output signal (quiescent 50% of VCC), also used for programming; requires load of at least 4.7 kΩ and at most 10 nF to GND. |
| 3 | GND | power_in | Ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOT-23W |
| Category | Sensors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Forward Supply Voltage | VCC | 8 | V | 2 | |||
| Reverse Supply Voltage | VRCC | -0.1 | V | 2 | |||
| Forward Output Voltage | VOUT | 15 | V | 2 | |||
| Reverse Output Voltage | VROUT | -0.1 | V | 2 | |||
| Output Source Current | IOUT(SOURCE) | 2 | mA | VOUT to GND | 2 | ||
| Output Sink Current | IOUT(SINK) | 10 | mA | VCC to VOUT | 2 | ||
| Operating Ambient Temperature | TA | -40 | 150 | ºC | L temperature range | 2 | |
| Maximum Junction Temperature | TJ(max) | 165 | ºC | 2 | |||
| Storage Temperature | Tstg | -65 | 170 | ºC | 2 | ||
| Package Thermal Resistance LH, 4-layer | RθJA | 228 | ºC/W | Package LH, on 4-layer PCB with copper limited to solder pads | 3 | ||
| Package Thermal Resistance LH, 2-layer | RθJA | 110 | ºC/W | Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side, connected by thermal vias | 3 | ||
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| Supply Current | ICC | 6.9 | 9 | mA | No load on VOUT | 4 | |
| Supply Zener Clamp Voltage | VZ | 6 | 8.3 | V | TA = 25°C, ICC = 12 mA | 4 | |
| Quiescent Voltage Output | VOUT(Q) | 2.425 | 2.5 | 2.575 | V | B = 0 G, TA = 25°C | 4 |
| Output Load Resistance | RL | 4.7 | kΩ | VOUT to VCC | 4 | ||
| Output Load Capacitance | CL | 10 | nF | VOUT to GND | 4 | ||
| Output Saturation Voltage High | VOUT(sat)HIGH | 4.7 | V | RPULLDOWN = 4.7 kΩ, VCC = 5 V | 4 | ||
| Output Saturation Voltage Low | VOUT(sat)LOW | 0.3 | V | RPULLUP = 4.7 kΩ, VCC = 5 V | 4 | ||
| Sensitivity | Sens | 2.375 | 2.5 | 2.625 | mV/G | A1326, TA = 25°C | 4 |
| Sensitivity Drift at Max Ambient Operating Temperature | ∆Sens(TAmax) | -5 | 5 | % | LH package; from hot to room temperature | 4 | |
| Sensitivity Drift at Min Ambient Operating Temperature | ∆Sens(TAmin) | -3.5 | 8.5 | % | LH package; from cold to room temperature | 4 | |
| Quiescent Voltage Output Drift Through Temperature Range | ∆VOUT(Q) | -10 | 10 | G | Defined in terms of magnetic flux density, B | 5 | |
| Linearity Sensitivity Error | LinERR | -1.5 | 1.5 | % | 5 | ||
| Symmetry Sensitivity Error | SymERR | -1.5 | 1.5 | % | 5 | ||
| Ratiometry Quiescent Voltage Output Error | RatVOUT(Q) | -1.3 | 1.3 | % | Throughout supply voltage range (relative to VCC = 5 V) | 5 | |
| Ratiometry Sensitivity Error | RatSens | -1.5 | 1.5 | % | Throughout supply voltage range (relative to VCC = 5 V), TA = 25°C and 150°C | 5 | |
| Ratiometry Sensitivity Error | RatSens | -2 | 2 | % | Throughout supply voltage range (relative to VCC = 5 V), TA = -40°C | 5 | |
| Power-On Time | tPO | 32 | µs | TA = 25°C, CL (PROBE) = 10 pF | 4 | ||
| Internal Bandwidth | BWi | 17 | kHz | Small signal, -3 dB | 4 | ||
| Chopping Frequency | fC | 400 | kHz | TA = 25°C | 4 | ||
| Output Referred Noise | VN | 3.5 | mV(p-p) | A1326, TA = 25°C, CBYPASS = 0.1 µF | 4 | ||
| Input Referred RMS Noise Density | VNRMS | 1.3 | mG/√Hz | TA = 25°C, CBYPASS = open, no load on VOUT, f << BWi | 4 | ||
| Sensitivity Temperature Coefficient | TCSens | 0 | %/°C | LH package; programmed at TA = 150°C, calculated relative to Sens at 25°C | 4 | ||
| Sensitivity Drift Due to Package Hysteresis | ∆SensPKG | 2 | % | TA = 25°C, after temperature cycling (printed ±2) | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | (UA), and a 3-pin surface mount SOT-23 style package (LH). Both are lead (Pb) free, with 100% matte tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A1326LLHLX-T - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23W (KiCad packages3D, STEP)
- 3D model files:
a1326llhlx-t-etched.step/a1326llhlx-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a1326llhlx-t.step/a1326llhlx-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (13 pp, sha256
6f43a734822c0281, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).