AT32F425F8P7 from ARTERY, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT0	input	Dedicated boot mode select pin 0 with a built-in weak pull-down that cannot be disabled; together with user system data bit nBOOT1 it selects the boot source at startup.
2	PF0	bidirectional	Standard-level (TC) I/O with input voltage limited to VSS-0.3 to 4.0 V, not 5 V tolerant; alternate function TMR1_CH1, additional function HEXT_IN.
3	PF1	bidirectional	Standard-level (TC) I/O with input voltage limited to VSS-0.3 to 4.0 V, not 5 V tolerant; alternate functions TMR1_CH2C, SPI2_CS and I2S2_WS, additional function HEXT_OUT.
4	NRST	bidirectional	Active-low device reset input and internal reset output with an internal pull-up (RPU 30 to 50 kΩ) that cannot be disconnected; VIL max 0.8 V and VIH min 2 V.
5	VDDA	power_in	Analog supply for the ADC, 2.4 to 3.6 V, which must be at the same potential as VDD.
6	PA0	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN0 and WKUP1.
7	PA1	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN1.
8	PA2	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN2 and WKUP4, and USART2_TX is used for bootloader.
9	PA3	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN3, and USART2_RX is used for bootloader.
10	PA4	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN4.
11	PA5	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN5.
12	PA6	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN6.
13	PA7	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN7.
14	PB1	bidirectional	FTa I/O that is 5 V tolerant only in input float, pull-up or pull-down mode (in analog mode the input must stay below VDD+0.3 V); provides ADC1_IN9.
15	VSS	power_in	Digital ground pin.
16	VDD	power_in	Digital supply pin, 2.4 to 3.6 V, supplying GPIO, ERTC, LEXT, BPR and the internal LDO.
17	PA9 (PA11)	bidirectional	TC-type I/O that is not 5 V tolerant on TSSOP20; default function PA9 (USART1_TX, TMR15_BRK, I2C1_SCL), and when OTGFS1 is not used PA11 can be remapped onto this pin by software, while OTGFS1_D- takes over the pin when OTGFS1 is enabled.
18	PA10 (PA12)	bidirectional	TC-type I/O that is not 5 V tolerant on TSSOP20; default function PA10 (USART1_RX, TMR17_BRK, I2C1_SDA), and when OTGFS1 is not used PA12 can be remapped onto this pin by software, while OTGFS1_D+ takes over the pin when OTGFS1 is enabled.
19	PA13	bidirectional	5 V tolerant FT I/O that after reset is configured as SWDIO with its internal pull-up enabled; alternate functions include IR_OUT, OTGFS1_OE and I2C1_SDA.
20	PA14	bidirectional	5 V tolerant FT I/O that after reset is configured as SWCLK with its internal pull-down enabled; alternate functions include USART2_TX, SPI3_MOSI and I2C1_SMBA.

Key specifications

Parameter	Value
Manufacturer	ARTERY
Package	TSSOP-20
Category	Single Chip Microcomputer/Microcontroller
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External main supply voltage VDDx-VSS	VDDx-VSS	-0.3		4	V		33
Voltage difference between supply pins /ΔVDDx/	/ΔVDDx/			50	mV		33
Voltage difference between ground pins /VSSx-VSS/	/VSSx-VSS/			50	mV		33
Total external supply current IVDD (incl. VDDA and VDD)	IVDD			150	mA		33
Total current through VSS ground line (outflow)	IVSS			150	mA		33
Output sink current on any GPIO and control pin	IIO			25	mA		33
Output current on any GPIO and control pin		-25			mA		33
Storage temperature range TSTG	TSTG	-60		150	°C		33
Maximum junction temperature TJ	TJ			125	°C		33
Supply voltage VDD (2.4 V to 3.6 V power supply)	VDD	2.4		3.6	V		1
Operating ambient temperature range		-40		105	°C		1
CPU maximum operating frequency				96	MHz		1
HEXT crystal oscillator frequency		4		25	MHz		1
HICK 48 MHz internal clock frequency accuracy		-1		1	%	25 °C	1
HICK 48 MHz internal clock frequency accuracy		-2		2	%	-40 °C to +105 °C	1
ADC analog supply voltage VDDA	VDDA	2.4		3.6	V		58
ADC current in VDDA input pin IDDA	IDDA		295	355	μA		58
ADC clock frequency fADC	fADC	0.6		28	MHz		58
ADC sampling rate fS	fS	0.05		2	MHz		58
ADC external trigger frequency fTRIG	fTRIG			1.65	MHz	fADC = 28 MHz	58
ADC internal sample-and-hold capacitance CADC	CADC		8.5	13	pF		58
ADC sampling time tS	tS	0.053		8.55	μs	fADC = 28 MHz	58
ADC total conversion time tCONV (incl. sampling time)	tCONV	0.5		9	μs	fADC = 28 MHz	58
ADC trigger conversion latency tlatr	tlatr			71.4	μs	fADC = 28 MHz	58
OTGFS operating voltage VDD	VDD	3		3.6	V		57
OTGFS transceiver startup time tSTARTUP	tSTARTUP			1	μs		57
OTGFS differential input sensitivity VDI	VDI	0.2			V		57
OTGFS differential common-mode range VCM	VCM	0.8		2.5	V	includes VDI range	57
OTGFS single-ended receiver threshold VSE	VSE	1.3		2	V		57
OTGFS static output low level VOL	VOL			0.3	V	1.24 kΩ RL to 3.6 V	57
OTGFS static output high level VOH	VOH	2.8		3.6	V	15 kΩ RL to VSS	57
OTGFS_D+ internal pull-up resistance RPU	RPU	0.97	1.24	1.58	kΩ	VIN = VSS	57
OTGFS_D+/D- internal pull-down resistance RPD	RPD	15	19	25	kΩ	VIN = VDD	57
OTGFS data rise time tr	tr	4		20	ns	CL ≤ 50 pF	57
OTGFS data fall time tf	tf	4		20	ns	CL ≤ 50 pF	57
OTGFS rise/fall time matching tr/tf	trfm	90		110	%		57
OTGFS output signal crossover voltage VCRS	VCRS	1.3		2	V		57
I2C standard mode maximum SCL frequency				100	kHz	standard mode	56
I2C fast mode maximum SCL frequency				400	kHz	fast mode	56
I2C enhanced fast mode maximum SCL frequency				1	MHz	enhanced fast mode	56

CAD (KiCad official)

Symbol: AT32F425F8P7
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: at32f425f8p7-etched.step / at32f425f8p7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f425f8p7.step / at32f425f8p7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY datasheet (79 pp, sha256 eaf33a9399a9b187, retrieved 2026-11-05, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AT32F425F8P7

Verified AT32F425F8P7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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