component
ADP7142AUJZ-3.3-R7
Public Made by Adomby adom
Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TSOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADP7142AUJZ-3.3-R7
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-23-5
ADP7142AUJZ-3.3-R7 from Analog Devices, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Regulator input supply, operating from 2.7 V to 40 V; bypass VIN to GND with a 2.2 µF or greater capacitor. |
| 2 | GND | power_in | Ground reference for the regulator. |
| 3 | EN | input | Enable pin: drive high to turn the regulator on and low to turn it off, and connect to VIN for automatic startup; precision enable thresholds are 1.15 V to 1.30 V (logic high) and 1.06 V to 1.18 V (logic low). |
| 4 | SENSE/ADJ | input | Sense input connects to the load, and an external resistor divider on this pin can set the output above the fixed voltage (ADJ); the pin is rated −0.3 V to +6 V to GND. |
| 5 | VOUT | power_out | Regulated output voltage; bypass VOUT to GND with a 2.2 µF or greater capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | 40 | V | 3 | ||
| Operating supply current | IGND | 50 | 140 | µA | IOUT = 0 µA | 3 | |
| Operating supply current | IGND | 80 | 190 | µA | IOUT = 10 mA | 3 | |
| Operating supply current | IGND | 180 | 320 | µA | IOUT = 200 mA | 3 | |
| Shutdown current | IGND-SD | 3 | 10 | µA | EN = GND, VIN = 40 V | 3 | |
| Output voltage accuracy | VOUT | -0.8 | 0.8 | % | IOUT = 10 mA, TJ = 25°C | 3 | |
| Output voltage accuracy | VOUT | -1.2 | 1.5 | % | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V, TJ = −40°C to +85°C | 3 | |
| Output voltage accuracy | VOUT | -1.8 | 1.8 | % | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V | 3 | |
| Line regulation | ∆VOUT/∆VIN | -0.01 | 0.01 | %/V | VIN = (VOUT + 1 V) to 40 V | 3 | |
| Load regulation | ∆VOUT/∆IOUT | 0.002 | 0.004 | %/mA | IOUT = 100 μA to 200 mA | 3 | |
| Sense input bias current | SENSEI-BIAS | 10 | 1000 | nA | 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V | 3 | |
| Dropout voltage | VDROPOUT | 30 | 60 | mV | IOUT = 10 mA | 3 | |
| Dropout voltage | VDROPOUT | 200 | 420 | mV | IOUT = 200 mA | 3 | |
| Current-limit threshold | ILIMIT | 250 | 360 | 460 | mA | 3 | |
| Precision EN logic high threshold | ENHIGH | 1.15 | 1.22 | 1.3 | V | 3 | |
| Precision EN logic low threshold | ENLOW | 1.06 | 1.12 | 1.18 | V | 3 | |
| EN leakage current | IEN-LKG | 0.04 | 1 | µA | EN = VIN or GND | 3 | |
| Minimum input and output capacitance | CMIN | 1.5 | µF | TA = −40°C to +125°C | 4 | ||
| Capacitor effective series resistance (ESR) | RESR | 0.001 | 0.3 | Ω | TA = −40°C to +125°C | 4 | |
| VIN to GND | VIN | -0.3 | 44 | V | 5 | ||
| VOUT to GND | VOUT | -0.3 | V | 5 | |||
| EN to GND | EN | -0.3 | 44 | V | 5 | ||
| SENSE/ADJ to GND | SENSE/ADJ | -0.3 | 6 | V | 5 | ||
| SS to GND | SS | -0.3 | V | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Operating ambient temperature range | TA | -40 | 125 | °C | 5 | ||
| ESD Human Body Model (5-Lead TSOT) | HBM | -1000 | 1000 | V | 5 | ||
| ESD Field Induced Charged Device Model (5-Lead TSOT) | FICDM | -1250 | 1250 | V | 5 | ||
| Junction-to-ambient thermal resistance (5-Lead TSOT) | θJA | 170 | °C/W | 4-layer board per JESD51-7/JESD51-9 | 5 | ||
| Junction-to-board thermal characterization parameter (5-Lead TSOT) | ΨJB | 43 | °C/W | 5 | |||
| Typical junction-to-ambient thermal resistance (5-Lead TSOT, 50 mm² copper) | θJA | 152 | °C/W | Copper size 50 mm² | 17 | ||
| Typical junction-to-ambient thermal resistance (5-Lead TSOT, 100 mm² copper) | θJA | 146 | °C/W | Copper size 100 mm² | 17 | ||
| Typical junction-to-ambient thermal resistance (5-Lead TSOT, 500 mm² copper) | θJA | 131 | °C/W | Copper size 500 mm² | 17 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | copper used to solder the package GND pins to the PCB. | 17 |
CAD (KiCad official)
- Symbol:
ADP7142AUJZ-3.3-R7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
adp7142aujz-3-3-r7-etched.step/adp7142aujz-3-3-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp7142aujz-3-3-r7.step/adp7142aujz-3-3-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
8b64fff54265a3cb, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).