TPD4S014DSQR from Texas Instruments, in a WSON-10-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBUSOUT	power_out	Switched output of the internal nFET to the downstream circuits; connect to an internal PCB plane, with recommended operating input range -0.1 V to 5.5 V and 10 µF capacitance.
2	VBUSOUT	power_out	Switched output of the internal nFET to the downstream circuits; connect to an internal PCB plane, with recommended operating input range -0.1 V to 5.5 V and 10 µF capacitance.
3	EN	input	Active-low enable input: drive EN low to enable the switch and high (1 V to 6 V) to disable it, with absolute maximum voltage of 6 V.
4	ACK	output	Open-drain adapter-voltage indicator output, driven low 17 ms (typ) after VIN is stable between UVLO and OVLO, requiring a 10 kΩ pullup to the host logic I/O voltage.
5	ID	bidirectional	ESD-protected line with reverse stand-off voltage of 5 V and ESD protection to ±15 kV contact and air-gap discharge.
6	D-	bidirectional	ESD-protected USB data line with reverse stand-off voltage of 5 V and low capacitance of 1.6 pF to GND.
7	D+	bidirectional	ESD-protected USB data line with reverse stand-off voltage of 5 V and low capacitance of 1.6 pF to GND.
8	GND	power_in	Ground reference for the device; connect to a low-impedance ground plane stitched near the GND pins to dissipate ESD events.
9	VBUS	power_in	USB input power connector side of VBUS, rated for input voltage protection up to 28 V DC with absolute maximum of 30 V.
10	VBUS	power_in	USB input power connector side of VBUS, rated for input voltage protection up to 28 V DC with absolute maximum of 30 V.
11	Central PAD	unconnected	Exposed thermal pad that is electrically disconnected from the device and must be used as a heat sink connected to a large GND plane pad on the PCB.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WSON-10-EP(2x2)
Category	Global Sourcing Parts
Pins	11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Maximum junction temperature		-40		150	°C		5
Max Voltage on VBUS		-0.5		30	V		5
Continuous current through nFET				2.6	A		5
Continuous current through ACK		-50		50	mA		5
Max Current through D+, D-, ID, VBUS ESD clamps				50	mA		5
Max voltage on EN, ACK, D+, D-, ID, VBUSOUT				6	V		5
Storage temperature	Tstg	-65		150	°C		5
Operating free-air temperature	TA	-40		85	°C		5
Input voltage VBUSOUT	VI	-0.1		5.5	V	VBUSOUT	5
Input voltage VBUS	VI	-0.1		5.5	V	VBUS	5
Input voltage EN	VI	-0.1		5.5	V	EN	5
Input voltage ACK	VI	-0.1		5.5	V	ACK	5
Input voltage D+, D-, ID	VI	-0.1		5.5	V	D+, D-, ID	5
VBUS continuous current	IVBUS			2	A	VBUSOUT	5
Junction-to-ambient thermal resistance	RθJA		70.3		°C/W		6
Junction-to-case (top) thermal resistance	RθJCtop		46.3		°C/W		6
Junction-to-board thermal resistance	RθJB		33.8		°C/W		6
Junction-to-top characterization parameter	ψJT		2.9		°C/W		6
Junction-to-board characterization parameter	ψJB		33.5		°C/W		6
Junction-to-case (bottom) thermal resistance	RθJCbot		16.3		°C/W		6
High-level input voltage	VIH	1			V	EN, Load current = 50 µA	6
Low-level input voltage	VIL			0.5	V	EN, Load current = 50 µA	6
Input Leakage Current	ILEAK			1	µA	EN, D+, D-, ID; VIO = 3.3 V	6
Low-level output voltage	VOL			0.1	V	ACK, IOL = 2 mA	6
Diode forward Voltage	VD		0.95		V	D+, D-, ID pins; lower clamp diode IO = 8 mA	6
Differential Capacitance between the D+, D- lines	ΔCIO		0.03		pF		6
Capacitance to GND for the D+, D- lines	CIO		1.6		pF	ƒ = 1 MHz	6
Capacitance to GND for the ID line	CIO-ID		19		pF		6
Reverse stand-off voltage of D+, D- and ID pins	VR		5		V		6
Breakdown voltage D+, D-, ID pins	VBR	6			V	IBR = 1 mA	6
VBUS Breakdown voltage on VBUS	VBR	28			V	IBR = 1 mA	6
Dynamic on resistance D+, D-, ID clamps	RDYN		1		Ω	II = 1 A	6
Under-voltage lock-out, input power detected threshold rising	VUVLO+	2.65	2.8	3	V	VBUS increasing from 0 V to 5 V, No load on OUT pin	7
Under-voltage lock-out, input power detected threshold falling	VUVLO-	2.25	2.44	2.7	V	VBUS decreasing from 5 V to 0 V, No load on OUT pin	7
Hysteresis on UVLO	VHYS-UVLO	150	360	550	mV	Δ of VUVLO+ and VUVLO-	7
VBUS switch resistance	RDS_VBUSSWITCH		151	200	mΩ	VBUS = 5 V, IOUT = 500 mA	7
Turn-ON time	tON	16	17.4	22	ms	VBUS increasing from 2.8 V to 4.75 V, EN = 0 V, RL = 36 Ω, CL = 10 uF	7
Turn-OFF time	tOFF		8		µs	VBUS decreasing from 2.44 V to 0.5 V, EN = 0V, RL = 36 Ω, CL = 10 uF	7
Input over-voltage protection threshold rising	VOVP+	5.9	6.15	6.45	V	VBUS increasing from 5 V to 7 V, No Load	7
Input over-voltage protection threshold falling	VOVP-	5.75	5.98	6.24	V	VBUS decreasing from 7 V to 5 V, No Load	7
Hysteresis on OVP	VHYS-OVP	25	100	275	mV	Δ of VOVP+ and VOVP-	7
Over voltage delay	td(OVP)		11		µs	RL = 36 Ω, CL = 10 µF; VBUS increasing from 5 V to 7 V	7
Recovery time from input over voltage condition	tREC		8	10.5	ms	RL = 36 Ω, CL = 10 µF; VBUS decreasing from 7 V to 5 V	7
VBUS Operating Current Consumption	IVBUS		147.6	160	µA	No load on VBUS_OUT pin, VBUS = 5 V, EN = 0 V	7
VBUS Operating Current Consumption (EN high)	IVBUS_OFF		111.8	120	µA	No load on VBUS_OUT pin, VBUS = 5 V, EN = 5 V	7
Thermal Shutdown	TSHDN		144		°C		7
Thermal-Shutdown Hysteresis	TSHDN-HYS		23		°C		7

CAD (KiCad official)

Symbol: TPD4S014DSQR
Footprint: Package_DFN_QFN:Texas_DSQ0010A_WSON-10-1EP_2x2mm_P0.4mm_EP0.9x1.5mm
3D model: WSON-10-EP(2x2) (KiCad packages3D, STEP)
3D model files: tpd4s014dsqr-etched.step / tpd4s014dsqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpd4s014dsqr.step / tpd4s014dsqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 c9cbfbb5333284ff, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPD4S014DSQR

Verified TPD4S014DSQR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README