component
HGC5615IM
Public Made by Adomby adom
HGSEMI Digital To Analog Converters (DAC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHGC5615IM
HGSEMI · Digital To Analog Converters (DAC) · SOP-8
HGC5615IM from HGSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Serial data input; the 16-bit word is clocked in most significant bit first on the rising edge of SCLK while CS is low. |
| 2 | SCLK | input | Serial clock input that shifts data into the input register on its rising edge; CS transitions should occur while SCLK is low. |
| 3 | CS | input | Chip select, active low; data is read in while CS is low and the rising edge of CS transfers the data to the DAC register. |
| 4 | DOUT | output | Serial data output for daisy chaining; DIN data appears at DOUT delayed by 16 clock cycles plus one clock width. |
| 5 | AGND | power_in | Analog ground; the recommended ground connection is to the system analog ground plane, with a 0.1µF ceramic bypass between VDD and AGND. |
| 6 | REFIN | input | Reference input (buffered, high impedance) that sets the DAC full-scale output at 2 times the reference voltage; Vref range is 2V to VDD-2V. |
| 7 | OUT | output | DAC analog voltage output, rail-to-rail buffered with short-circuit protection, which can drive a 2k load with 100pF load capacitance. |
| 8 | VDD | power_in | Positive power supply, 4.5V to 5.5V (5V nominal) referenced to AGND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-8 |
| Category | Data Acquisition |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral nonlinearity, end point adjusted (INL) | INL | -1 | 1 | LSB | Vref=2.048V | 5 | |
| Differential nonlinearity (DNL) | DNL | -0.5 | 0.1 | 0.5 | LSB | Vref=2.048V | 5 |
| Zero-scale error (offset error at zero scale) | EZS | -3 | 3 | LSB | Vref=2.048V | 5 | |
| Gain error | EG | -3 | 3 | LSB | Vref=2.048V | 5 | |
| Voltage output range | VO | 0 | V | RL= 10k | 6 | ||
| Output voltage, low-level | VOL(low) | 0.25 | V | IO(OUT)≤5mA | 6 | ||
| Output voltage, high-level | VOH(high) | 4.75 | V | IO(OUT)≤- 5mA | 6 | ||
| Input voltage (REFIN) | VI | 0 | V | 6 | |||
| High-level digital input voltage | VIH | 2.4 | V | 6 | |||
| Low-level digital input voltage | VIL | 0.8 | V | 6 | |||
| High-level digital input current | IIH | -1 | 1 | µA | VI = VDD | 6 | |
| Low-level digital input current | IIL | -1 | 1 | µA | VI = 0 | 6 | |
| Output voltage, low-level (DOUT) | VOL | 0.4 | V | IO = 2mA | 6 | ||
| Supply voltage | VDD | 4.5 | 5 | 5.5 | V | 6 | |
| Power supply current | IDD | 150 | 250 | µA | VDD = 5.5V, No load, All inputs=0V or VDD, Vref = 0 | 6 | |
| Power supply current | IDD | 230 | 350 | µA | VDD = 5.5V, No load, All inputs=0V or VDD, Vref = 2.048V | 6 | |
| Setup time, DIN before SCLK high | tsu(DS) | 45 | ns | 6 | |||
| Hold time, DIN valid after SCLK high | th(DH) | 0 | ns | 6 | |||
| Setup time, CS low to SCLK high | tsu(CSS) | 1 | ns | 6 | |||
| Setup time, CS high to SCLK high | tsu(CS1) | 50 | ns | 6 | |||
| Hold time, SCLK low to CS low | th(CSH0) | 1 | ns | 6 | |||
| Hold time, SCLK low to CS high | th(CSH1) | 0 | ns | 6 | |||
| Pulse duration, minimum chip select pulse width high | tw(CS) | 20 | ns | 6 | |||
| Pulse duration, SCLK low | tw(CL) | 25 | ns | 6 | |||
| Pulse duration, SCLK high | tw(CH) | 25 | ns | 6 | |||
| Supply voltage (VDD to AGND) | VDD | 7 | V | 4 | |||
| Digital input voltage range to AGND | -0.3 | V | 4 | ||||
| Reference input voltage range to AGND | -0.3 | V | 4 | ||||
| Continuous current at any terminal | 20 | mA | 4 | ||||
| Operating free-air temperature range, TA (HGC5615I) | TA | -40 | 85 | °C | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature | 260 | °C | 1.6mm (1/16 inch) from case for 10 seconds | 4 | |||
| Supply voltage, VDD | VDD | 4.5 | 5 | 5.5 | V | 4 | |
| High-level digital input voltage | VIH | 2.4 | V | 4 | |||
| Low-level digital input voltage | VIL | 0.8 | V | 4 | |||
| Reference voltage, Vref to REFIN terminal | Vref | 2 | 2.048 | V | 4 | ||
| Load resistance | RL | 2 | kΩ | 4 | |||
| Operating free-air temperature, TA (HGC5615I) | TA | -40 | 85 | °C | 4 |
CAD (KiCad official)
- Symbol:
HGC5615IM - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
hgc5615im-etched.step/hgc5615im-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hgc5615im.step/hgc5615im.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (19 pp, sha256
4f15d178132b78e6, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).