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TPS7A0512PDBZR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS7A0512PDBZR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23
TPS7A0512PDBZR from Texas Instruments, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. This pin must be connected to ground on the board. |
| 2 | OUT | output | Regulated output pin. A capacitor is required from OUT to ground for stability, using the value listed in the Recommended Operating Conditions table, placed as close to the output as possible. |
| 3 | IN | input | Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table, placed as close to the input as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal accuracy | -1 | 1 | % | VOUT ≥ 1.0 V, TJ = 25°C | 7 | ||
| Accuracy over temperature | -2 | 2 | % | VOUT ≥ 1.0 V, TJ = -40°C to +85°C | 7 | ||
| Accuracy over temperature | -3 | 3 | % | VOUT ≥ 1.0 V | 7 | ||
| Line regulation | ΔVOUT(ΔVIN) | 5 | 16.5 | mV | VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V, TJ = -40°C to +85°C | 7 | |
| Line regulation | ΔVOUT(ΔVIN) | 18 | mV | VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V | 7 | ||
| Load regulation (DBZ) | ΔVOUT(ΔIOUT) | 27 | 50 | mV | 100 μA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V, TJ = -40°C to +85°C | 7 | |
| Load regulation (DBZ) | ΔVOUT(ΔIOUT) | 62 | mV | 100 μA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + VDO(max) + 0.1 V | 7 | ||
| Ground current | IGND | 0.6 | 1 | 1.3 | µA | TJ = 25°C, IOUT = 1 µA | 7 |
| Ground current | IGND | 2 | µA | IOUT = 1 µA, TJ = -40°C to +85°C | 7 | ||
| Ground current | IGND | 3 | µA | IOUT = 1 µA | 7 | ||
| Shutdown current | ISHDN | 100 | 300 | nA | VEN = 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, TJ = 25°C | 7 | |
| Output current limit | ICL | 210 | 450 | 700 | mA | VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V | 7 |
| Output current limit | ICL | 250 | 450 | 700 | mA | VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V, TJ = 0°C to +85°C | 7 |
| Short-circuit current limit | ISC | 65 | 150 | mA | VOUT = 0 V | 7 | |
| UVLO threshold (rising) | VUVLO | 1.21 | 1.3 | 1.37 | V | VIN rising | 8 |
| UVLO threshold (falling) | VUVLO | 1.17 | 1.33 | V | VIN falling | 8 | |
| EN pin logic high voltage | VEN(HI) | 0.9 | V | 8 | |||
| EN pin logic low voltage | VEN(LO) | 0.4 | V | 8 | |||
| Absolute maximum input voltage | -0.3 | 6 | V | Voltage on IN pin with respect to GND | 6 | ||
| Absolute maximum output voltage | -0.3 | V | Max: VIN + 0.3 V or 3.6 V (whichever is smaller), with respect to GND | 6 | |||
| Absolute maximum enable voltage | -0.3 | V | Max: VIN + 0.3 V, with respect to GND | 6 | |||
| Operating junction temperature (absolute maximum) | TJ | -40 | 125 | °C | 6 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Input supply voltage | VIN | 1.4 | 5.5 | V | 6 | ||
| Enable supply voltage | VEN | 0 | V | Max: VIN | 6 | ||
| Nominal output voltage range | VOUT | 0.8 | 3.3 | V | 6 | ||
| Output current | IOUT | 0 | 200 | mA | 6 | ||
| Output capacitor | COUT | 0.47 | 1 | 22 | µF | 6 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Input capacitor | CIN | 1 | µF | 6 | |||
| Enable pulldown resistor | RPULLDOWN | 120 | Ω | VIN = 3.3 V, P version only | 8 | ||
| Thermal shutdown temperature (shutdown) | Tsd | 160 | °C | Shutdown, temperature increasing | 8 | ||
| Thermal shutdown temperature (reset) | Tsd | 140 | °C | Reset, temperature decreasing | 8 | ||
| Junction-to-ambient thermal resistance | RθJA | 267.3 | °C/W | DBZ (SOT-23) package | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 103.5 | °C/W | DBZ (SOT-23) package | 6 | ||
| Junction-to-board thermal resistance | RθJB | 98 | °C/W | DBZ (SOT-23) package | 6 | ||
| Junction-to-top characterization parameter | ΨJT | 9.2 | °C/W | DBZ (SOT-23) package | 6 | ||
| Junction-to-board characterization parameter | YJB | 97.4 | °C/W | DBZ (SOT-23) package | 6 |
CAD (KiCad official)
- Symbol:
TPS7A0512PDBZR - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
tps7a0512pdbzr-etched.step/tps7a0512pdbzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a0512pdbzr.step/tps7a0512pdbzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (56 pp, sha256
4e552a784da45faa, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).