TPS563202DRLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-563. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownTPS563202DRLR
Texas Instruments · DC-DC Converters · SOT-563
TPS563202DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage supply pin. Operating input range 4.3 V to 17 V (abs-max 19 V). Bypass to GND with a low-ESR ceramic capacitor placed close to the pin. |
| 2 | SW | output | Switch node connection between the integrated high-side and low-side NFETs. Connect to the output inductor. Operating range −1.8 V to 17 V (abs-max −2 V to 19 V). |
| 3 | GND | power_in | Ground pin. Source terminal of the low-side power NFET and the return for the controller circuit. Connect sensitive FB to this GND at a single point. |
| 4 | BST | power_out | Bootstrap supply for the high-side NFET gate driver. Connect a 0.1-µF ceramic capacitor between BST and SW. Absolute-max 25 V to GND, 6.5 V relative to SW. |
| 5 | EN | input | Enable input control. Active high; must be pulled high to enable the device (V_ENH ≥ 1.35 V typ, V_ENL ≤ 1.05 V typ). Internal pull-down R_EN ≈ 400 kΩ. Do not float. |
| 6 | FB | input | Converter feedback input. Connect the output voltage through a resistor divider to set V_OUT (V_FBTH ≈ 0.806 V in continuous mode, 0.815 V typ in Eco-mode). Very low input bias current (0 typ, ±0.1 µA max). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
TPS563202DRLR
CAD (KiCad official)
- Symbol:
TPS563202DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps563202drlr-etched.step/tps563202drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps563202drlr.step/tps563202drlr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps563202drlr.step |
448 KB | You want the bare part, or you mark your own boards. |
tps563202drlr-etched.step |
2.9 MB | You want the part with TPS563202DRLR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 622 faces against 54 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
7863c4bb81a64fb5, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).