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KSZ8061MNGW

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Microchip Tech Ethernet ICs, TQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8061mngwfactory-2.0.0extractor-text

Verified KSZ8061MNGW

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: KSZ8061MNGW · TQFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 66-page datasheet
  • ✓distributor: lcsc C633466, digikey KSZ8061MNGW-ND, mouser 579-KSZ8061MNGW
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-khn_d5p3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ksz8061mngw.kicad_sym✓ ksz8061mngw.kicad_mod✓ ksz8061mngw.step
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Contents

README

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KSZ8061MNGW

Microchip Tech · Ethernet ICs · TQFN-48-EP(7x7)

KSZ8061MNGW from Microchip Tech, in a TQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XI input Crystal/oscillator/external clock input, 25 MHz ±50 ppm, referenced to the AVDDH supply.
2 XO output Crystal feedback output for the 25-MHz crystal; no connect if an oscillator or external clock source is used.
3 AVDDH power_in 3.3V supply for analog TX drivers and XI/XO oscillator circuit.
4 GND power_in Ground.
5 TXP bidirectional Physical transmit or receive signal (+ differential).
6 TXM bidirectional Physical transmit or receive signal (- differential).
7 GND power_in Ground.
8 RXP bidirectional Physical receive or transmit signal (+ differential).
9 RXM bidirectional Physical receive or transmit signal (- differential).
10 GND power_in Ground.
11 GND power_in Ground.
12 AVDDL power_in 1.2V (nominal) supply for analog core.
13 GND power_in Ground.
14 VDDL power_in 1.2V (nominal) supply for digital core.
15 COL/B-CAST_OFF bidirectional MII collision detect output; strap-in latched at reset deassertion, pull-up makes PHY address 0 unique, pull-down (default) makes it broadcast.
16 MDIO bidirectional Management interface (MIIM) data I/O with weak pull-up, open-drain like, requires external 1.0-kΩ pull-up resistor.
17 MDC input Management interface (MIIM) clock input, synchronous to MDIO, with internal pull-up.
18 RXER/QWF bidirectional MII receive error output; strap-in latched at reset: pull-up disables Quiet-Wire filtering, pull-down (default) enables it.
19 RXDV/CONFIG2 bidirectional MII receive data valid output; latched at reset deassertion as CONFIG2.
20 RXD3/PHYAD0 bidirectional MII receive data output [3]; latched at reset deassertion as PHYADDR[0].
21 GND power_in Ground.
22 VDDIO power_in 3.3V, 2.5V, or 1.8V supply for digital I/O.
23 RXD2/PHYAD1 bidirectional MII receive data output [2]; latched at reset deassertion as PHYADDR[1].
24 RXD1/PHYAD2 bidirectional MII receive data output [1]; latched at reset deassertion as PHYADDR[2].
25 RXD0/DUPLEX bidirectional MII receive data output [0]; latched at reset as DUPLEX (pull-up default = half-duplex, pull-down = full-duplex).
26 RXC/CONFIG0 bidirectional MII receive clock output; latched at reset deassertion as CONFIG0.
27 VDDL power_in 1.2V (nominal) supply for digital core.
28 GND power_in Ground.
29 TXC output MII transmit clock output.
30 TXEN input MII transmit enable input.
31 TXD0 input MII transmit data input [0], synchronous to TXC.
32 TXD1 input MII transmit data input [1], synchronous to TXC.
33 VDDIO power_in 3.3V, 2.5V, or 1.8V supply for digital I/O.
34 TXER input MII transmit error input with internal pull-down; may be unconnected if the MAC does not provide TXER.
35 TXD2 input MII transmit data input [2], synchronous to TXC.
36 GND power_in Ground.
37 TXD3 input MII transmit data input [3], synchronous to TXC.
38 CRS/CONFIG1 bidirectional MII carrier sense output; latched at reset deassertion as CONFIG1 (also NAND tree output).
39 LED0/AUTONEG bidirectional Active-low LED0 output, default link/activity; latched at reset as AUTONEG (pull-up default enables auto-negotiation).
40 LED1/SPEED bidirectional Active-low LED1 output, default link speed; latched at reset as SPEED (pull-up default = 100 Mbps, pull-down = 10 Mbps).
41 VDDIO power_in 3.3V, 2.5V, or 1.8V supply for digital I/O.
42 RESET# input Chip reset, active low, with internal pull-up.
43 GND power_in Ground.
44 INTRP/NAND_Tree# bidirectional Programmable interrupt output (active low default or active high), open drain like, requires external 1.0-kΩ pull-up; latched at reset as NAND_Tree# (pull-down enables NAND tree).
45 VDDL power_in 1.2V (nominal) supply for digital (and analog).
46 GND power_in Ground.
47 REXT input Sets PHY transmit output current; connect a 6.04-kΩ 1% resistor from this pin to ground.
48 SIGDET output Signal detect output, active high.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

CAD (KiCad official)

  • Symbol: KSZ8061MNGW
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: TQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ksz8061mngw-etched.step / ksz8061mngw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8061mngw.step / ksz8061mngw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (66 pp, sha256 0e29337b489edbaf, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF