component
ADS7924IRTER
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADS7924IRTER
Texas Instruments · Analog To Digital Converters (ADC) · VQFN-16-EP(3x3)
ADS7924IRTER from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | input | External reset input, active low. |
| 2 | INT | output | Interrupt output, active low by default, generated when the input voltage is beyond the programmed threshold. |
| 3 | SCLK | input | I2C serial clock input; the ADS7924 is slave only and never drives SCL. |
| 4 | SDA | bidirectional | I2C serial data line, used for both transmitting and receiving data. |
| 5 | A0 | input | I2C address select; tied to ground gives address 1001000 and tied to DVDD gives address 1001001. |
| 6 | DGND | power_in | Digital ground; DGND to AGND is limited to ±0.3 V. |
| 7 | PWRCON | output | Power control output used to shut down and power up an external operational amplifier. |
| 8 | AGND | power_in | Analog ground. |
| 9 | CH3 | input | Multiplexer analog input channel 3, with the analog input voltage limited to AGND ±0.3 V. |
| 10 | CH2 | input | Multiplexer analog input channel 2, with the analog input voltage limited to AGND ±0.3 V. |
| 11 | CH1 | input | Multiplexer analog input channel 1, with the analog input voltage limited to AGND ±0.3 V. |
| 12 | CH0 | input | Multiplexer analog input channel 0, with the analog input voltage limited to AGND ±0.3 V. |
| 13 | MUXOUT | output | Multiplexer output, routed externally so one signal conditioning circuit can be shared between the MUX and ADC. |
| 14 | ADCIN | input | ADC input, fed from the external signal path after MUXOUT. |
| 15 | AVDD | power_in | Analog supply, 2.2 V to 5.5 V relative to AGND, also used as the ADC reference; AVDD must be at least DVDD. |
| 16 | DVDD | power_in | Digital supply, 1.65 V up to AVDD. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Data Acquisition |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, AVDD to AGND | -0.3 | 6 | V | 4 | |||
| Supply voltage, DVDD to DGND | -0.3 | 6 | V | 4 | |||
| AGND to DGND | -0.3 | 0.3 | V | 4 | |||
| Digital input voltage with respect to DGND (SCL and SDA) | 6 | V | 4 | ||||
| Input current to all pins except supply pins | -10 | 10 | mA | 4 | |||
| Maximum operating temperature | -40 | 85 | °C | 4 | |||
| Storage temperature | -60 | 150 | °C | 4 | |||
| Electrostatic discharge, Human-body model (HBM) | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Electrostatic discharge, Charged-device model (CDM) | V(ESD) | -750 | 750 | V | Charged-device model (CDM), per JEDEC specification JESD22-C101 | 4 | |
| AVDD Analog Supply Voltage | AVDD | 2.2 | 5.5 | V | Over operating free-air temperature range | 4 | |
| DVDD Digital Supply Voltage | DVDD | 1.65 | V | Over operating free-air temperature range | 4 | ||
| Full-scale input span (CHX, AGND) | 0 | V | 5 | ||||
| Integral linearity | -1.5 | 0.5 | 1.5 | LSBs | 5 | ||
| Differential linearity | -1 | 0.6 | 1.5 | LSBs | 5 | ||
| Offset error | -5 | 5 | LSBs | 5 | |||
| Gain error | -0.2 | -0.01 | 0.2 | % | 5 | ||
| Internal clock frequency variation | -20 | 20 | % | 5 | |||
| Logic level VIL (SDA, SCL, A0, RESET) | VIL | 0.4 | V | 5 | |||
| Input current | II | -10 | 10 | μA | VI = DVDD or DGND | 5 | |
| Logic level VOL (PWRCON, INT, SDA) | VOL | 0.4 | V | IOL = 100 μA | 5 | ||
| Specified performance temperature range | -40 | 85 | °C | 5 | |||
| Power-supply voltage DVDD | DVDD | 1.65 | 5.5 | V | 5 | ||
| Power-supply voltage AVDD | AVDD | 2.2 | 5.5 | V | 5 | ||
| Power-down current | IPWRD | 1 | μA | 5 | |||
| Analog supply current IAVDD | IAVDD | 5 | 8 | μA | tCYCLE = 2.5 ms, AVDD = 2.2 V | 5 | |
| Fast I2C SCL operating frequency | fSCL | 0 | 0.4 | MHz | 6 | ||
| Bus free time between START and STOP condition | tBUF | 1.3 | μs | 6 | |||
| Hold time after repeated START condition | tHDSTA | 600 | ns | 6 | |||
| Repeated START condition setup time | tSUSTA | 600 | ns | 6 | |||
| Stop condition setup time | tSUSTO | 600 | ns | 6 | |||
| Data hold time | tHDDAT | 0 | ns | 6 | |||
| Data setup time | tSUDAT | 100 | ns | 6 | |||
| SCL clock low period | tLOW | 1300 | ns | 6 | |||
| SCL clock high period | tHIGH | 600 | ns | 6 | |||
| Clock/data fall time | tF | 300 | ns | 6 | |||
| Clock/data rise time | tR | 300 | ns | 6 | |||
| Data valid time | tVDDAT | 0.9 | μs | 6 | |||
| Data valid acknowledge time | tVDACK | 0.9 | μs | 6 | |||
| Pulse width of spike suppressed by input filter | tSP | 0 | 50 | ns | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 48.1 | °C/W | RTE (WQFN), 16 pins | 4 | ||
| Junction-to-case(top) thermal resistance | RθJC(top) | 47.3 | °C/W | RTE (WQFN), 16 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 60.8 | °C/W | RTE (WQFN), 16 pins | 4 | ||
| Junction-to-top characterization parameter | ψJT | 0.3 | °C/W | RTE (WQFN), 16 pins | 4 | ||
| Junction-to-board characterization parameter | ψJB | 14.1 | °C/W | RTE (WQFN), 16 pins | 4 | ||
| Junction-to-case(bottom) thermal resistance | RθJC(bot) | 0.4 | °C/W | RTE (WQFN), 16 pins | 4 | ||
| Input capacitance | 4 | 10 | pF | CH0 to CH3 input pin | 5 | ||
| ADC sampling capacitance | 15 | pF | 5 | ||||
| MUX resistance | 60 | Ω | 5 | ||||
| Input channel crosstalk | 85 | dB | 5 | ||||
| Resolution | 12 | Bits | 5 | ||||
| No missing codes | 12 | Bits | 5 | ||||
| Offset error drift | 0.01 | LSB/°C | 5 | ||||
| Gain error drift | 0.6 | ppm/°C | 5 | ||||
| Noise (rms) | 0.125 | LSB | 5 | ||||
| Monitoring time/channel | 10 | µs | 5 | ||||
| Low-level output current IOL (SDA pin) | IOL | 3 | mA | SDA pin, VOL = 0.6 V | 5 | ||
| Load capacitance CB (SDA pin) | CB | 400 | pF | SDA pin | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor for AVDD close to the device AVDD pin and connect this capacitor to the device pins with thick copper | 41 |
CAD (KiCad official)
- Symbol:
ADS7924IRTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ads7924irter-etched.step/ads7924irter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads7924irter.step/ads7924irter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
f680e98ab6f72d72, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).