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RAA2142504GSP#HA0
Public Made by Adomby adom
RENESAS Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRAA2142504GSP#HA0
RENESAS · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP
RAA2142504GSP#HA0 from RENESAS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | VOUT is the regulated output voltage pin that supplies power to the load, and a minimum 2.2µF X5R/X7R output capacitor is required between this pin and GND for stable operation. |
| 2 | VOUT | power_out | VOUT is the regulated output voltage pin that supplies power to the load, and a minimum 2.2µF X5R/X7R output capacitor is required between this pin and GND for stable operation. |
| 3 | ADJ | input | ADJ is internally set to 1.224V by the band-gap circuit, and an external voltage divider on this pin sets the output voltage; shorting it to VOUT sets the output to the minimum 1.224V. |
| 4 | NC | unconnected | The datasheet pin description table does not define the function of this pin. |
| 5 | GND | power_in | GND is the ground pin and must be tied to GND. |
| 6 | EN | input | EN is the enable input: a LOW level turns the LDO off and a HIGH level turns it on, and it should not be left floating but tied to the VIN pins for automatic enabling. |
| 7 | VIN | power_in | VIN is an input voltage pin that supplies the LDO, and Renesas recommends a 10µF and 1µF input capacitor from this pin to GND with the 1µF placed as close as possible to the VIN pins. |
| 8 | VIN | power_in | VIN is an input voltage pin that supplies the LDO, and Renesas recommends a 10µF and 1µF input capacitor from this pin to GND with the 1µF placed as close as possible to the VIN pins. |
| 9 | EPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage | VOUT | 1.2 | 18 | V | 6 | ||
| Input Voltage | VIN | 2.5 | 20 | V | 6 | ||
| Reference Voltage Accuracy | VREF | -1.7 | 1.7 | % | VIN = 2.5V to 20V, T = 25°C | 6 | |
| Reference Voltage Accuracy | VREF | -2 | 2 | % | T = -40°C to 125°C | 6 | |
| Line Regulation | ∆VOUT/∆VIN | 0.02 | 0.05 | %/V | VIN = VOUT+1V to 20V | 6 | |
| Dropout Voltage | VDO | 269 | 450 | mV | IOUT = 500mA, VOUT = 3.3V | 6 | |
| Shutdown Current | ISHDN | 5.8 | 13 | µA | VEN = 0, VIN = 20V | 6 | |
| Ground Current | IGND | 140 | 225 | µA | IOUT = 500mA, VIN = 2.5V, VEN = 5V | 6 | |
| EN Rising Threshold | 1.35 | 1.5 | 1.65 | V | 6 | ||
| Short Circuit Current Limit | 240 | 600 | mA | With Foldback, VIN - VOUT = 18V | 6 | ||
| Supply Voltage | VIN | 2.5 | 20 | V | 5 | ||
| Enable Input Voltage | EN | 0 | 20 | V | 5 | ||
| Output Voltage | VOUT | 0 | 18 | V | 5 | ||
| Adjustable Pin Voltage | ADJ | 0 | 5 | V | 5 | ||
| Output Current | IOUT | 0 | 500 | mA | 5 | ||
| Output Capacitor | COUT | 1 | 200 | µF | 5 | ||
| Junction Temperature | -40 | 125 | °C | 5 | |||
| Supply Voltage | VIN | -0.3 | 22 | V | 5 | ||
| Enable Input Voltage | EN | -0.3 | 22 | V | 5 | ||
| Output Voltage | VOUT | -0.3 | 22 | V | 5 | ||
| Adjustable Pin Voltage | ADJ | -0.3 | 6 | V | 5 | ||
| Output Current | IOUT | 500 | mA | 5 | |||
| Maximum Junction Temperature | -40 | 125 | °C | 5 | |||
| Maximum Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Human Body Model | 2 | kV | Tested per JS-001-2017 | 5 | |||
| Charged Device Model | 750 | V | Tested per JS-002-2018 | 5 | |||
| Latch-Up | 100 | mA | Tested per JESD78E; Class 2, Level A | 5 | |||
| Thermal Resistance Junction to Ambient (8 Ld EPSOIC) | θJA | 58 | °C/W | 8 Ld EPSOIC, junction to ambient, free air | 5 | ||
| Thermal Resistance Junction to Case (8 Ld EPSOIC) | θJC | 16 | °C/W | 8 Ld EPSOIC, case = center of exposed metal pad | 5 |
CAD (KiCad official)
- Symbol:
RAA2142504GSP#HA0 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
raa2142504gsp-ha0-etched.step/raa2142504gsp-ha0-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);raa2142504gsp-ha0.step/raa2142504gsp-ha0.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (35 pp, sha256
15f07d7a0df493ab, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).