LTC6820HMS#PBF from Analog Devices, in a MSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Device enable input: high forces the LTC6820 to stay enabled overriding IDLE mode, low allows IDLE after 5.7ms of inactivity, with wake-up less than 8µs after CS falls or a signal on IP/IM.
2	MOSI	bidirectional	SPI master out/slave in data: input from the master controller when MSTR is high, open-drain output to the slave when MSTR is low, requiring an external pull-up to VDDS.
3	MISO	bidirectional	SPI master in/slave out data: open-drain output to the master controller when MSTR is high, input from the slave when MSTR is low, requiring an external pull-up to VDDS.
4	SCK	bidirectional	SPI clock: input from the master (not to be pulled above VDDS) when MSTR is high, push-pull output to the slave when MSTR is low with no pull-up needed.
5	CS	bidirectional	SPI chip select: input from the master (not to be pulled above VDDS) when MSTR is high, push-pull output to the slave when MSTR is low with no pull-up needed.
6	VDDS	power_in	SPI I/O power supply (1.7V to 5.5V) that sets the SCK/CS output drive and the SCK, CS, MOSI, MISO and EN input thresholds; may be tied to VDD or level shifted, with a bypass capacitor of at least 0.01µF to GND if separate from VDD.
7	POL	input	SPI clock polarity input, tied to VDD or GND.
8	PHA	input	SPI clock phase input, tied to VDD or GND.
9	VDD	power_in	Device power supply input (2.7V to 5.5V) requiring a bypass capacitor of at least 0.01µF directly between VDD and GND.
10	IM	bidirectional	Isolated interface minus input/output.
11	IP	bidirectional	Isolated interface plus input/output.
12	MSTR	input	Master/slave selector input: tie to VDD on the master side of the isolated interface, tie to GND on the slave side.
13	SLOW	input	Slow interface selection input: tie to VDD for clock frequencies at or below 200kHz or if slaves cannot meet timing, tie to GND for clock frequencies above 200kHz.
14	GND	power_in	Device ground.
15	ICMP	input	Isolated interface comparator threshold set: tie to the resistor divider between IBIAS and GND, with comparator thresholds set to 1/2 the voltage on ICMP.
16	IBIAS	passive	Isolated interface current bias: tie to GND through a resistor divider, pin is about 2V when enabled, IP/IM sink current is 20 times the IBIAS current, and capacitance should be limited to less than 50pF.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-16
Category	Interface ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating Supply Voltage Range	VDD	2.7		5.5	V		3
IO Supply Voltage Range (Level Shifting)	VDDS	1.7		5.5	V	Affects CS, SCK, MOSI, MISO and EN Pins	3
Supply Current, IDLE State (slave)	IDD		2	6	µA	MSTR = 0V	3
Supply Current, IDLE State (master)	IDD		1	3	µA	MSTR = VDD	3
IO Supply Current	IDDS			1	µA	SPI Inputs and EN Pin at 0V or VDDS, SPI Outputs Unloaded	3
Voltage on IBIAS Pin	VBIAS	1.9	2	2.1	V	READY/ACTIVE State	3
Isolated Interface Current Gain	AIB	18	20	22	mA/mA	VA ≤ 1.6V, IB = 1mA	3
Isolated Interface Current Gain	AIB	18	20	24	mA/mA	VA ≤ 1.6V, IB = 0.1mA	3
Threshold-Setting Voltage on ICMP Pin	VICMP	0.2		1.5	V	VTCMP = ATCMP • VICMP	3
Leakage Current on ICMP Pin	ILEAK(ICMP)	-1		1	µA	VICMP = 0V to VDD	3
Leakage Current on IP and IM Pins	ILEAK(IP/IM)	-2		2	µA	IDLE State, VIP = VIM = 0V to VDD	3
Receiver Comparator Threshold Voltage Gain	ATCMP	0.4	0.5	0.6	V/V	VCM = VDD/2 to VDD, 0.2V, VICMP = 0.2V to 1.5V	3
Receiver Input Resistance	RIN	26	35	42	kΩ	Single-Ended to IP or IM	3
Differential Wake-Up Voltage	VWAKE			240	mV	tDWELL = 240ns	3
Dwell Time at VWAKE	tDWELL			240	ns	VWAKE = 240mV	3
Start-Up Time After Wake Detection	tREADY			8	µs		3
Idle Time-Out Duration	tIDLE	4	5.7	7.5	ms		3
Digital Voltage Input High, Configuration Pins (PHA, POL, MSTR, SLOW)	VIH(CFG)	0.7			×VDD	VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW)	3
Digital Voltage Input Low, Configuration Pins (PHA, POL, MSTR, SLOW)	VIL(CFG)			0.3	×VDD	VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW)	3
Digital Voltage Input High, SPI Pins	VIH(SPI)	0.7			×VDDS	VDDS = 2.7V to 5.5V	3
Digital Voltage Input High, SPI Pins	VIH(SPI)	0.8			×VDDS	VDDS = 1.7V to 2.7V	3
Digital Voltage Input Low, SPI Pins	VIL(SPI)			0.3	×VDDS	VDDS = 2.7V to 5.5V	3
Digital Voltage Input Low, SPI Pins	VIL(SPI)			0.2	×VDDS	VDDS = 1.7V to 2.7V	3
Digital Voltage Input High, EN Pin	VIH(EN)	2			V	VDDS = 2.7V to 5.5V	3
Digital Voltage Input High, EN Pin	VIH(EN)	0.85			×VDDS	VDDS = 1.7V to 2.7V	3
Digital Voltage Input Low, EN Pin	VIL(EN)			0.8	V	VDDS = 2.7V to 5.5V	3
Digital Voltage Input Low, EN Pin	VIL(EN)			0.25	×VDDS	VDDS = 1.7V to 2.7V	3
Digital Voltage Output Low (MOSI, MISO, CS, SCK)	VOL			0.2	V	VDDS = 3.3V, Sinking 3.3mA	3
Digital Pin Input Leakage Current	ILEAK(DIG)	-1		1	µA	PHA, POL, MSTR, SLOW = 0V to VDD; CS, SCK, MOSI, MISO, EN = 0V to VDDS	4
Chip-Select Half-Pulse Width	t1/2PW(CS)	120	150	180	ns		4
Chip-Select Pulse Inversion Delay	tINV(CS)			200	ns		4
Chip-Select Response Delay	tDEL(CS)		140	190	ns		4
Data Half-Pulse Width	t½PW(D)	40	50	60	ns		4
Data Pulse Inversion Delay	tINV(D)			70	ns		4
Data Response Delay	tDEL(D)		75	120	ns		4
SCK Latching Edge to SCK Latching Edge	tCLK	0.5			µs	SLOW = 0	4
SCK Latching Edge to SCK Latching Edge	tCLK	5			µs	SLOW = 1	4
MOSI Setup Time Before SCK Latching Edge	t1	25			ns		4
MOSI Hold Time After SCK Latching Edge	t2	25			ns		4
isoSPI Data Recognized to SCK Latching Edge	t12	110	145	185	ns	SLOW = 0	4
SCK Pulse Width	t13	90	115	150	ns	SLOW = 0	4
SCK Non-Latch Edge to isoSPI Data Transmit	t14	115	145	190	ns	SLOW = 0	4
CS Falling Edge to SCK Non-Latch Edge	t15	90	120	160	ns	PHA = 1 SLOW = 0	4
CS Falling Edge to isoSPI Data Transmit	t16	200	265	345	ns	SLOW = 0	4
CS Rising Edge to SCK Latching Edge	t17	90	120	160	ns	PHA = 1 SLOW = 0	4
CS Rising Edge to MOSI Rising Edge	t18			35	ns		4
Input Supply Voltages (VDD and VDDS) to GND				6	V		2
Pin Voltage SCK, CS, EN		-0.3		6	V	-0.3V to VDDS + 0.3V (6V Max)	2
Pin Voltage IBIAS, SLOW, IP, IM		-0.3		6	V	-0.3V to VDD + 0.3V (6V Max)	2
Pin Voltage All Other Pins		-0.3		6	V		2
Maximum Source/Sink Current MOSI, MISO, SCK, CS				20	mA		2
Operating Temperature Range LTC6820H		-40		125	°C		2
Storage Temperature Range		-65		150	°C		2
Maximum Junction Temperature	TJMAX			150	°C	MS package	2
Thermal Resistance Junction to Ambient	θJA		120		°C/W	MS package, 16-lead MSOP	2
Input/Output Pin Capacitance	CI/O		10		pF	Note 9	4

CAD (KiCad official)

Symbol: LTC6820HMS#PBF
Footprint: Package_SO:MSOP-16_3x4.039mm_P0.5mm
3D model: MSOP-16 (KiCad packages3D, STEP)
3D model files: ltc6820hms-pbf-etched.step / ltc6820hms-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc6820hms-pbf.step / ltc6820hms-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (30 pp, sha256 81e209e79f6c137d, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LTC6820HMS#PBF

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3D Model

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