component
TPS54116QRTWTQ1
Public Made by Adomby adom
Texas Instruments Power Management Specialized - PMIC, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54116QRTWTQ1
Texas Instruments · Power Management Specialized - PMIC · WQFN-24-EP(4x4)
TPS54116QRTWTQ1 from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switching node of the buck converter. |
| 2 | BOOT | passive | Bootstrap capacitor node for the high-side MOSFET gate driver; connect the bootstrap capacitor from this pin to the SW pin. |
| 3 | AVIN | power_in | Input supply to the IC powering the control circuits of both the buck converter and DDR termination regulator; connect to a supply between 2.95 V and 6 V. |
| 4 | ENSW | input | Buck converter enable with internal pull-up current source; floating enables the IC, below 1.17 V enters standby, below 0.4 V enters shutdown, and two resistors can set adjustable UVLO. |
| 5 | ENLDO | input | VTT LDO enable with internal pull-up current source; floating enables the IC, below 1.17 V enters standby, below 0.4 V enters shutdown, and two resistors can set adjustable UVLO. |
| 6 | PGOOD | output | Open-drain power good indicator for the buck regulator; a 10-kΩ pull-up to AVIN or an external logic supply is recommended. |
| 7 | VDDQSNS | input | VDDQ sense input used to generate the VDDQ/2 reference for VTTREF. |
| 8 | LDOIN | power_in | Power supply input for the VTT LDO, connected to VDDQ in the typical application or a lower voltage in split-rail configuration to reduce power dissipation. |
| 9 | VTT | power_out | 1-A LDO output; connect 2 x 10-µF ceramic capacitors to VTTGND for stability. |
| 10 | VTTGND | power_in | Power ground for the VTT LDO. |
| 11 | VTTSNS | input | VTT LDO voltage feedback. |
| 12 | VTTREF | power_out | Buffered low-noise VTT reference output; connect a 0.22 µF or larger ceramic capacitor to AGND for stability. |
| 13 | ILIM | input | Programmable current limit pin; the high-side MOSFET peak current limit is set by an external resistor to AGND. |
| 14 | AGND | power_in | Analog signal ground of the IC; connect to PGND at a single point on the PCB, typically at the thermal pad. |
| 15 | FB | input | Error amplifier inverting input for buck voltage regulation; connect to the center of a resistor divider from the output voltage to AGND. |
| 16 | COMP | passive | Output of the internal transconductance error amplifier for the buck converter; the loop compensation network is connected from this pin to AGND. |
| 17 | SS/TRK | passive | Soft-start programming pin; a capacitor to AGND sets the soft-start time, and its voltage overrides the internal reference for tracking and sequencing. |
| 18 | RT/SYNC | input | Resistor timing and external clock pin; a resistor to AGND sets the switching frequency, and pulling above the upper threshold switches it to a synchronization clock input. |
| 19 | PGND | power_in | Power ground of the buck regulator; connect to AGND at a single point on the PCB, typically at the thermal pad. |
| 20 | PGND | power_in | Power ground of the buck regulator; connect to AGND at a single point on the PCB, typically at the thermal pad. |
| 21 | PVIN | power_in | Input supply for the power MOSFETs; connect to a supply between 2.95 V and 6 V. |
| 22 | PVIN | power_in | Input supply for the power MOSFETs; connect to a supply between 2.95 V and 6 V. |
| 23 | SW | output | Switching node of the buck converter. |
| 24 | SW | output | Switching node of the buck converter. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage AVIN, PVIN | V(AVIN), V(PVIN) | 2.95 | 6 | V | 5 | ||
| Buck output voltage | VOUT | 0.6 | 4.5 | V | 5 | ||
| Buck output current | IOUT | 0 | 4 | A | 5 | ||
| VDDQSNS input voltage | V(VDDQSNS) | 1 | 3.5 | V | 5 | ||
| LDOIN input voltage | V(LDOIN) | 3.5 | V | min is VTT + VDO | 5 | ||
| VTT and VTTREF output voltage | V(VTT), V(VTTREF) | 0.5 | 3.5 | V | 5 | ||
| Abs max PVIN, AVIN, ENSW, ENLDO, PGOOD | -0.3 | 7 | V | 4 | |||
| Abs max FB, COMP, SS/TRK, ILIM | -0.3 | 3 | V | 4 | |||
| Abs max RT/SYNC voltage | -0.3 | 6 | V | 4 | |||
| Abs max BOOT with respect to SW | -0.3 | 7 | V | 4 | |||
| Abs max LDOIN, VTTSNS, VDDQSNS | -0.3 | 3.6 | V | 4 | |||
| Abs max SW | -0.6 | 7 | V | 4 | |||
| Abs max SW 10-ns transient | -4 | 10 | V | 10-ns transient | 4 | ||
| Abs max VTT, VTTREF | -0.3 | 3.6 | V | 4 | |||
| Abs max RT/SYNC current | -100 | 100 | µA | 4 | |||
| Abs max PGOOD current | -5 | 5 | mA | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| AVIN and PVIN operating | 2.95 | 6 | V | 5 | |||
| AVIN internal UVLO threshold | 2.7 | 2.8 | V | AVIN rising | 5 | ||
| AVIN internal UVLO hysteresis | 0.05 | 0.12 | V | 5 | |||
| Iq shutdown | Iq | 1 | 3.5 | µA | V(ENSW) = V(ENLDO) = 0 V, V(VDDQSNS) = 1.8 V, TJ = 25°C | 5 | |
| Iq operating, LDO and buck enabled | Iq | 650 | 800 | µA | V(ENSW) = V(ENLDO) = V(AVIN) = 5 V, V(FB) = 0.7 V, V(VDDQSNS) = 1.8 V, TJ = 25°C | 5 | |
| Iq operating, LDO enabled, buck disabled | Iq | 190 | 300 | µA | V(ENLDO) = V(AVIN) = 5 V, V(ENSW) = 0 V, V(VDDQSNS) = 1.8 V, TJ = 25°C | 5 | |
| Iq operating, LDO disabled, buck enabled | Iq | 570 | 700 | µA | V(ENSW) = V(AVIN) = 5 V, V(ENLDO) = 0 V, V(FB) = 0.7 V, V(VDDQSNS) = 1.8 V, TJ = 25°C | 5 | |
| Voltage Reference | VREF | 0.594 | 0.6 | 0.606 | V | 6 | |
| Error Amp transconductance | gmEA | 260 | 360 | µS | -2 µA < I(COMP) < 2 µA, V(COMP) = 1 V | 6 | |
| High side switch resistance | 33 | 66 | mΩ | V(BOOT-SW) = 5 V | 6 | ||
| High side switch resistance | 42 | 84 | mΩ | V(BOOT-SW) = 3.3 V | 6 | ||
| Low side switch resistance | 25 | 50 | mΩ | V(PVIN) = 5 V | 6 | ||
| Low side switch resistance | 30 | 60 | mΩ | V(PVIN) = 3.3 V | 6 | ||
| High-side FET current limit | 5.2 | 6.6 | 8.2 | A | V(PVIN) = 6V, R(ILIM) = 100k | 6 | |
| High-side FET current limit | 1.5 | 3 | 3.8 | A | V(PVIN) = 6V, R(ILIM) = 200k | 6 | |
| Switching frequency | 370 | 400 | 430 | kHz | R(RT/SYNC) = 150 kΩ | 6 | |
| Switching frequency | 1910 | 2070 | 2230 | kHz | R(RT/SYNC) = 27 kΩ | 6 | |
| Switching frequency | 340 | 420 | 480 | kHz | V(RT/SYNC) > 2.2 V or V(RT/SYNC) < 0.35 V | 6 | |
| SS/TRK charge current | ISS | 1.5 | 2.4 | 3.2 | µA | V(SS/TRK) > VSSTHR | 6 |
| PGOOD output high leakage | 5 | 125 | nA | V(FB) = VREF, V(PGOOD) = 5.5 V | 7 | ||
| PGOOD on resistance | 85 | 170 | Ω | V(AVIN) = 2.95 V | 7 | ||
| VDDQSNS input current | 39 | 46 | µA | V(VDDQSNS) = 1.8 V | 7 | ||
| VTTREF tolerance | V(VTTREF)TOL | -18 | 18 | mV | /I(VTTREF)/ < 10 mA, V(VDDQSNS) = 1.8 V | 7 | |
| VTTREF tolerance | V(VTTREF)TOL | -15 | 15 | mV | /I(VTTREF)/ < 10 mA, V(VDDQSNS) = 1.5 V | 7 | |
| VTTREF tolerance | V(VTTREF)TOL | -12 | 12 | mV | /I(VTTREF)/ < 5 mA, V(VDDQSNS) = 1.2 V | 7 | |
| VTT tolerance to VTTREF | V(VTT)TOL | -20 | 20 | mV | /I(VTT)/≤ 10 mA, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V | 7 | |
| VTT tolerance to VTTREF | V(VTT)TOL | -30 | 30 | mV | /I(VTT)/≤ 1 A, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V | 7 | |
| VTT tolerance to VTTREF | V(VTT)TOL | -40 | 40 | mV | /I(VTT)/≤ 1.5 A, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V | 7 | |
| VTT source current limit | I(VTT)SRC | 1.5 | 2.5 | A | V(VDDQSNS) = 1.8 V, V(VTT) = V(VTTSNS) = 0.7 V | 7 | |
| VTT sink current limit | I(VTT)SNK | 1.5 | 2.5 | A | V(VDDQSNS) = 1.8 V, V(VTT) = V(VTTSNS) = 1.1 V | 7 | |
| VTTSNS input bias current | I(VTTSNS)BIAS | -0.1 | 0.1 | µA | 7 | ||
| Thermal resistance junction-to-ambient | RθJA | 36.2 | °C/W | RTW (WQFN) 24 pins | 5 | ||
| Thermal resistance junction-to-case (top) | RθJC(top) | 35 | °C/W | 5 | |||
| Thermal resistance junction-to-board | RθJB | 14.3 | °C/W | 5 | |||
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | 4.6 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS54116QRTWTQ1 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps54116qrtwtq1-etched.step/tps54116qrtwtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54116qrtwtq1.step/tps54116qrtwtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
b4a1a1be1bccb59c, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).